Xilinx has announced the tape-out of the first Virtex UltraScale device. Based on the UltraScale architecture, and the industry’s only high-end 20nm offering, the Virtex UltraScale family combines improved levels of performance, system integration, and bandwidth for a wide range of applications. The architecture delivers customers an ASIC-class advantage by deploying multiple ASIC techniques and a new routing architecture to remove next generation interconnect and scalability bottlenecks.
The UltraScale architecture scales from 20nm planar through 16nm FinFET technologies and from monolithic through 3D ICs.
Based on TSMC’s 20SoC process, the first Virtex UltraScale device, called the VU095, features 940k logic cells plus six integrated 150G Interlaken and four 100G Ethernet cores—equivalent to an additional 833k logic cells. This device also features 32.75 Gb/s transceivers capable of chip-to-chip and chip-to-optics interfaces as well as the world’s first all programmable 28Gb/s backplane support.
“With the Virtex UltraScale 20nm family having no direct competition, and based on the industry’s only ASIC class architecture, only Xilinx is delivering the technology needed for next generation smart and high performance systems,” said Dave Myron, senior director of FPGA product management and marketing.
The Virtex UltraScale VU095 is intended for high-end wired communications infrastructure applications like 4x100G transponders and 4x100G MAC-to-Interlaken bridges, as well as applications in test and measurement, aerospace and defense, and high performance computing.