Xilinx extends UltraScale portfolio with ASIC-class architecture and ASIC-strength design solution

Xilinx is making available its 20nm All Programmable UltraScale portfolio with product documentation and Vivado Design Suite support. The company shipped its first 20nm silicon early in November 2013, and is looking to execute an aggressive UltraScale device rollout. These devices have been designed to provide ASIC-class performance but with the industrys only ASIC-class programmable architecture as well as being coupled with the Vivado design suite and the UltraFast design methodology.

The UltraScale product portfolio looks to extend the Kintex and Virtex FPGA and 3D IC families, based on the UltraScale architecture and the enhanced gate density of TSMCs 20SoC process. UltraScale devices enable 1.5x to 2x realisable system performance and integration, and consume up to half the power, relative to currently available solutions.

These devices deliver next generation routing, ASIC-like clocking, and enhancements to logic and fabric to eliminate interconnect bottlenecks while supporting consistent device utilization of more than 90% without performance degradation.

According to Moshe Gavrielov, president and CEO at Xilinx, UltraScale devices bring our customers ASIC-class capabilities by coupling our UltraScale ASIC-class architecture with our Vivado ASIC-strength design suite and UltraFast methodology. The combination of these silicon and design solutions enable the fastest path to achieve significant systems differentiation for our customers, and enables a far superior alternative to ASICs and ASSPs.

The new Kintex UltraScale FPGAs will be able to deliver up to 1.16M logic cells, 5,520 optimised DSP slices, 76 Mbits of BRAM, 16.3Gbps backplane-capable transceivers, PCIe Gen3 hard blocks, integrated 100Gb/s Ethernet MAC and 150Gb/s Interlaken IP Cores, and DDR4 memory interfaces.

Initially introduced as part of the 28nm Xilinx 7 series family, Kintex devices established the new mid-range category of best price-performance at the lowest power.

The new Virtex UltraScale devices combined enhanced performance, system integration and bandwidth on a single chip. The largest family member delivers 4.4M logic cells, 1,456 user I/Os, 48 x 16.3 Gb/s backplane-capable transceivers and 89 Mbits of Block RAM, breaking previous records by more than doubling Xilinxs industrys highest capacity Virtex-7 2000T device and delivering a staggering 50M equivalent ASIC gates.

Virtex UltraScale devices include 28Gb/s backplane-capable and 33Gb/s chip-to-optics transceivers, in addition to integrated PCIe Gen3, 100Gb/s Ethernet MAC and 150Gb/s Interlaken IP cores, and DDR4 memory interfaces to support multi-hundred gigabit-per-second levels of system performance with smart processing at full line rates.

These UltraScale devices provide the same performance of the logic fabric and key architectural blocks across the entire UltraScale portfolio, enabling a scalable and optimised architecture. Moreover, with footprint compatibility between families, Kintex UltraScale FPGAs provide a clear migration path to Virtex UltraScale devices.

Xilinx UltraScale devices are sampling now.



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