Xilinx’s All Programmable 7 series FPGAs and Zynq-7000 All Programmable SoCs have achieved full PCI Express compliance and are now listed on the PCI-SIG integrator’s list. All of Xilinx’s 28nm devices passed electrical, protocol and interoperability tests at the latest PCI-SIG event held in April this year. This marked PCI-SIG’s first official PCI Express Gen3 compliance and interoperability testing since the introduction of the specification.
By leveraging 7 series FPGA and Zynq-7000 All Programmable SoC integrated blocks for PCI Express Gen2 and Gen3, designers can meet high system bandwidth and programmable systems integration requirements needed in a variety of markets, including communications, storage and server applications.
Virtex-7 and Kintex-7 families support Gen3 (8 Gbps) with links for up to x8 for high throughput data centre applications, and Artix-7 FPGA and Zynq-7000 All Programmable SoC integrated blocks support Gen2 (5 Gbps) with links up to x4 and x8 respectively, enabling accelerated design productivity for low cost applications such as industrial and automotive.
“Xilinx remains at the forefront of the technology with its 28nm families as the market leader in FPGA-based PCI Express solutions since the protocol’s introduction,” said Ketan Mehta, PCI Express product marketing manager at Xilinx. “With the industry’s most robust auto-adaptive Decision Feedback Equalization (DFE) for link tuning and in-system non-destructive eye scan technology, and the Vivado Design Suite for accelerated integration and implementation our customers can achieve faster time-to-market with a PCI Express solution.”
With all 7 series FPGA and Zynq-7000 All Programmable SoC families currently shipping in volume production, designers can begin evaluating PCI Express Gen2 and Gen3 solutions immediately using targeted reference designs (TRDs), boards and kits available on www.xilinx.com. These kits include end-to-end connectivity and reference designs that offer DDR3, PCI Express Direct Memory Access (DMA) engines and Ethernet IP blocks. Additional soft IP cores are supported through Xilinx Alliance Program members, including Northwest Logic and PLDA.