CIE Components in Electronics
In an effort to address the increasing complexity that is associated with advanced node designs, Cadence Design Systems has announced that TSMC has expanded collaboration with Cadence on the Virtuoso custom and analogue design platform to design and verify its own cutting-edge IP. Additionally, TSMC has extended its native SKILL-based process design kits (PDKs) portfolio to 16 nanometers, creating and delivering fully qualified and high-quality native SKILL-based PDKs to enable all the leading-edge features of the Virtuoso platform.
To allow customers to fully maximize performance and quality of results, the new PDKs enable leading-edge features within the Virtuoso 12.1 platform, such as auto-alignment, automatic handling of complex rules during abutment, chaining devices, support of colour-aware layout, and advanced routing.
“We have continued our major investments in advancing the Virtuoso platform to address the ever mounting design challenges. We worked closely with TSMC and our customers to enhance and deliver on advanced node and mainstream design requirements,” said Dr. Chi-Ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence. “The high-quality native SKILL-based PDKs are key to powering up the Virtuoso methodologies to their full potential.”
“We have a long-term partnership with Cadence on the Virtuoso platform,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “The extension of SKILL-based PDK development to 16 nanometers allows us to better address customers’ needs in custom design of advanced technologies.”
