Toshiba Electronics Europe (TEE) has announced the availability of a Structured Array technology to European customers. The technology provides an ASIC alternative to FPGAs with lower cost and power consumption – but still at significantly lower implementation and sample/production turn-around time than standard ASICs, according to Toshiba.
Based on technology licensed from BaySand Inc., the Structured Arrays have been designed to support the rapid creation of high-performance, low-power system-on-chip (SoC) devices. This is achieved through the customisation of only a small number of metal mask layers on pre-designed and pre-manufactured base wafers with an optimised logic (gate array) and block memory structure. Minimising the number of metal layers that need to be customised has helped to reduce minimum sample delivery time to just five weeks and has a significant advantage on non-recurring engineering (NRE) costs.
SoCs created using Toshiba’s Structured Array technology are said to be able to offer reduced costs, lower power consumption and, if required, higher performance than FPGA alternatives. Structured array designs can be developed with verified RTL data from an FPGA and support FPGA compatibility in terms of memory and I/O architecture. In addition, FPGA package and pin layout compatibility supports “drop-in” replacement for FPGA components.
The new Structured Arrays use a 65nm process technology and support up to 30 million raw logic gates, 20Mbit of SRAM and a maximum of 1200 I/O pins. LVDS and DDR capabilities are available and options for Gigabit high-speed transceivers (up to 6.5Gbps) are being developed. A 40nm line-up is also under development, targeting high-speed transceivers up to 12.5Gbps.