Aldec, Inc., an industry leader in electronic design verification, has added a UVM Register Generator to the newest release of Riviera-PRO. It allows users to automate register model creation which not only saves time but also removes the risk of specific coding errors that can arise when manually creating UVM classes.
Within the UVM Register Generator, two kinds of input data will be supported, namely IP-XACT component files (part of IEE Std. 1685-2009/2014) and CSV files. “This is a great addition to an already highly capable and cost-effective EDA tool,” said Radek Nawrot, Riviera-PRO product manager. “It’s of immense benefit to be able to create an error-free and reusable UVM test environment as quickly and seamlessly as possible.”
Riviera-PRO now also includes Unit Linting. It enables designers to quickly perform quality checks on just the block (or ‘unit’) of code on which they are working without having to launch a separate application; though doing so remains possible. The Unit Lint function runs Aldec’s ALINT-PRO in the background and can be launched from within Riviera-PRO; provided the user has either the LVT edition of Riviera-PRO or a standalone license for the linter.
In addition, Riviera-PRO can now handle the latest extensions to the VHDL language – extensions which are likely to be included in the formal release of VHDL 2018.
“All three enhancements to Riviera-PRO were made at the request of customers,” continues Nawrot. “These customers are keen to improve their productivity and they want to start simulating designs coded in VHDL 2018 as soon as possible.”
Riviera-PRO 2018.02 includes numerous new features, usability enhancements, and performance optimisations.
Riviera-PRO 2018.02 highlights
- UVM Register Generator
- Unit Linting
- Initial support for VHDL 2018 (based on proposals for IEEE standard 1076-2018)
- Support for Verilog-AMS and mixed-signal simulation on Linux64
- MATLAB and Simulink Interface Enhancements
- New QEMU Bridge 2.10.0
- Precompiled Aldec AXI BFM 2.0
- Support for SystemVerilog net aliasing
- Support for SystemVerilog multidimensional packed arrays in unions
- Support for SystemVerilog force and release on part-selects from vectors
- Up to 1000 per cent speedup for simulation assertions-based project with multi clocks
- Simulation speed for SystemVerilog constrained random designs is now up to 25 per cent faster