99.5 per cent of engineers admit products have been delayed or completely derailed as a result of late stage design complications. That’s according to new research from the 6SigmaET team at Future Facilities, which examined current approaches to device design and the priority given to testing and analysis throughout the design process.
The research, which surveyed over 350 electronics engineers, also found that 32 per cent of them “regularly” have products delayed by late stage complications, while seven per cent have had the majority of their products delayed in this way. Six per cent even went as far as to say that they have had every single one of their projects delayed as a result of unexpected issues towards the end of the design process.
In identifying the reason for these late stage complications, 1 in 5 engineers claimed that unexpected thermal issues were a common cause for delays. According to 6SigmaET’s ‘Heat is On’ report, this may be due to the fact that more than a quarter (27 per cent) of design engineers do not test the thermal operation of their devices before the design stage is complete.
Commenting on these findings, Tom Gregory, product manager at 6SigmaET said, “For a long time now, we at 6SigmaET have been raising awareness for the problems associated with late stage design complications. Too many engineers leave the testing – including thermal testing – of their products until the very last minute, but the fact is that this is nearly always a bad idea.
“Relying on late-stage testing means that problems that would have been easy to fix in the early stages of a design end up being ignored until a product is almost ready for production. This can result in costly ‘back to the drawing board’ changes or inefficient work-arounds being added to paper over the cracks.
“Rather than waiting until the last minute to identify problems in their designs, electronics engineers need to do more testing at the earliest stages of a design. Using a combination of simulated models and device prototypes can ensure maximum efficiency of a device at all stages of the design process.”