Synopsys, Inc. has announced release of the latest versions of its circuit simulation and custom design products—HSPICE, FineSim SPICE, and CustomSim simulators and the Custom Compiler IC design tool—to address the growing need for robust custom design. The growth in automotive electronics and transition to FinFET process nodes have led to a significant increase in IC design complexity and the need for rigorous analysis to validate custom and analog/mixed-signal (AMS) designs across a broad spectrum of process corners and environmental conditions. The latest releases of Synopsys’ custom design solution provide 2X faster simulation and Monte Carlo analysis speed, as well as enhancements to Custom Compiler, including interactive device-level routing to accelerate robust custom design.
FinFET designs have significantly more post-layout parasitics, making transistor-level simulation of large analog and custom digital designs a formidable challenge. The 2017.12 release of FineSim SPICE delivers core engine innovations and RC optimisations to provide 2X speed-up for FinFET post-layout simulation of large designs.
To accelerate robust design validation, the latest release of FineSim SPICE also delivers 2X Monte Carlosimulation speed-up by streamlining Monte Carlo model generation and results post-processing. Similarly, new RC reduction and partitioning algorithms in the 2017.12 release of the CustomSim FastSPICE tool deliver 2X speed-up for post-layout SRAM simulation and maintain multi-core scalability by providing additional 2X speed-up on four cores. Additionally, the 2017.12 release of HSPICE delivers 1.5X speed-up for large post-layout designs.
Custom Compiler enhancements accelerate custom layout
Custom Compiler‘s industry-pioneering visually-assisted layout automation technologies provide a substantial boost to custom layout productivity, especially for FinFET process nodes. In the 2017.12 release, this feature set has been enhanced to include device-level pattern routing. Unlike typical routers, the pattern router in Custom Compiler creates connections that mimic interconnect patterns that a layout designer creates by hand. Achieving hand-crafted-quality routes is important for device-level connections, especially for sensitive analog circuitry.
Custom Compiler includes a library of built-in routing patterns. In addition, the pattern router can extract patterns from a hand-created layout and reapply those patterns to other connections that need to be routed. This new feature complements the previously released feature that enables placement patterns in the design to be reused. Now Custom Compiler can place and route devices automatically, following patterns learned from an example layout. We call this approach template-based design, a powerful way to accelerate custom layout by reusing layout knowledge.
“High-reliability applications, such as automotive and FinFET process node designs, pose new challenges for companies needing to ensure custom design robustness,” said Bijan Kiani, vice president of marketing at Synopsys. “The latest enhancements in Synopsys’ Custom Design Platform enable design teams to accelerate custom and AMS design and validation through innovations in visually-assisted layout automation and simulation performance technologies.”