Synopsys, Inc., has announced that STMicroelectronics selected and standardised on Synopsys VC Formal, as their formal verification solution for advanced microcontroller designs. VC Formal”s high performance, capacity and robust engines enabled ST to locate corner case bugs earlier in the design cycle, achieving significantly faster and earlier verification closure over existing solutions.
‘ST is the leading supplier of products and solutions for Smart Driving and the Internet of Things, fulfilling industry needs with its STM32 family of advanced 32-bit general-purpose microcontrollers,’ said Mirella Negro Marcigaglia, MCD Verification Group Manager at STMicroelectronics. ‘The comprehensive STM32 product portfolio addresses a broad diversity of application challenges with very aggressive market-introduction schedules. Designers need a formal verification solution so as to provide best-in-class performance and quality, on a timely basis. Synopsys VC Formal’s integrated formal verification and assertion IPs are very effective and exceeded our expectations in these areas, leading to significantly reducing development time.’
With its comprehensive set of formal applications (Apps), including Property Verification (FPV), Connectivity Checking (CC), Sequential Equivalence Checks (SEQ), Register Verification (FRV), Formal Coverage Analyser (FCA) and Automatic Extraction of Properties (AEP), Synopsys VC Formal has delivered faster property convergence for ST’s many different use cases. VC Formal’s broad portfolio of formal assertion IPs, led to the discovery of a significant number of pre-silicon bugs, enabling ST to deliver more designs in less time, without compromising quality. The native integration of VC Formal with Synopsys VCS functional verification solution and Verdi’s industry leading debug engines, allows design and verification teams to easily leverage formal technologies and automate root cause analysis of formal results. Additionally, the native integration of robust coverage engines of VCS in VC Formal, facilitates easy insertion of formal analysis into the existing verification environment.
‘We have long collaborated with industry leaders on the delivery of comprehensive static and formal verification solutions for advanced SoCs,’ said Mo Movahed, vice president of R&D in the Synopsys Verification Group. ‘Throughout these collaborations, we continue to build advanced formal verification solutions that integrate easily into verification flows and methodologies, enabling faster time to market.’
For more information on VC Formal, please visit our blog at https://blogs.synopsys.com/informal-chat/