Silicon Labs has expanded its PCI Express (PCIe) timing solution portfolio with new one- and two-output PCIe clock generators that are able to offer the smallest footprint and lowest power currently in the market. Designed to meet the stringent specifications of the PCIe Generation 1/2/3 standards, the Si52111 and Si52112 clock generator ICs target high-volume consumer, embedded, communications and enterprise applications where board space, power consumption and system cost are critical concerns.
The Si5211x clock generators are suited for space-constrained, power-sensitive consumer electronics products such as digital still cameras that require industry-standard PCIe connectivity. Addressing the small form factor requirements of these applications, the Si5211x clocks are available in a 3 mm x 3 mm 10-pin TDFN package – the smallest package available in the PCIe timing market. These ultra-low-power clock generators offer up to eight times lower current consumption (less than 15 mA) than competing devices, making it easier for designers to meet green power regulations while enhancing system reliability. The devices also meet PCIe jitter requirements with up to 50 percent margin, enabling a lower bit error rate to further improve reliability.
In addition to offering power savings and improved jitter margin, the Si5211x clock generators use an innovative push-pull output buffer technology. Compared to many existing solutions in the market, the Si5211x PCIe clock generators integrate all termination and reference resistors on chip, eliminating the need for additional external components. These highly integrated devices are intended to help system designers reduce the bill of materials, board space requirements and design complexity. Most competing solutions require up to four resistors per output clock, as well as a current source reference resistor. As an added benefit, on-chip integration of these resistors enables the designer to lay out a clean transmission line from the output of the Si5211x IC to the input of the receiver, simplifying board design and removing discontinuities in the clock transmission lines that can otherwise degrade signal integrity.
“The adoption of the PCIe interface standard in applications beyond network storage and servers has driven the need for small size, high integration and ultra-low power consumption in PCIe clock solutions,” said Mike Petrowski, vice president and general manager of Silicon Labs’ timing products. “Silicon Labs is addressing these application requirements with the industry’s smallest and lowest power PCIe clock generators available. Despite their tiny size, the Silicon Labs PCIe clock generators pack a lot of integrated features into a single-chip solution that greatly enhances signal integrity.”