The PCIe interconnect standard has been widely adopted in numerous applications including consumer electronics, blade servers, storage, embedded computing, IP gateways and industrial systems. The PCIe interface is also supported in FPGA and SoC devices. Silicon Labs has applied its patented mixed-signal technology to deliver a suite of flexible clocking solutions that enable PCIe design across varying market and application requirements.
“By applying our ‘one-stop-shop’ timing IC supplier model to the PCIe market, we’re providing customers with flexibility in choosing the right clocking solutions ,” said Mike Petrowski, general manager of Silicon Labs’ timing products. “We are now able to offer developers a full complement of off-the-shelf options for minimising power, enhancing signal integrity and reducing cost, as well as the industry’s most customizable clock generators and buffers for FPGA-based designs.”
The Si5214x clock generator and Si5315x clock buffer families consist of two- to nine-output timing devices that offer the industry’s highest level of performance per watt. The new PCIe clock generators and buffers are twice as power efficient as competing clocking solutions. Lower power helps minimize heat dissipation and reduces the need for additional cooling components and power regulators. The devices also meet PCIe jitter requirements with up to 50 percent margin, leading to better system reliability and enhanced bit-error-rate performance.
In a further aid to managing design complexity, the Si5214x and Si5315x devices use output buffer technology to integrate all external termination resistors, thereby reducing component count, BOM cost, board space and power. The smallest PCIe clocking devices on the market, the new clock generators and buffers are ideal for space-constrained applications.
To combat electromagnetic interference (EMI) and radio frequency interference (RFI), the Si5214x and Si5315x families feature programmable edge rate and skew controls for each individual output. Using a built-in I2C interface, developers can fine-tune signals and fix integrity issues on the fly without adding more components. This signal integrity tuning capability streamlines EMI compliance, speeding time to market for PCIe board designs.
Factory-customised, pin-controlled Si5335 devices are available in two weeks (without minimum order restrictions) and any combination of up to four output frequencies ranging from 1 to 350 MHz can be configured on the Si5335 outputs. Up to three unique device configurations can be specified for a single part number, enabling the Si5335 to replace three separate clock generators or buffers and allowing developers to reuse a custom Si5335 device across multiple designs.
The Si5335 clock generator/buffer IC features up to five user-assignable control pins to simplify PCIe and FPGA-based system design and streamline EMI compliance with its PCIe-compliant spread spectrum clocking option. The Si5335 device features Silicon Labs’ patented MultiSynth fractional divider technology, which enables any-frequency synthesis on every output clock with sub-picosecond jitter.
The Si5335 simplifies multi-chip clocking by supporting any combination of differential formats such as LVPECL, LVDS and CML and single-ended formats like LVCMOS.