As a result of this level of performance facilitates the design of software-based modems and associated application software, for multiple communication standards, in parallel and in a real-time environment. The SDK platform was defined in collaboration with a Tier 1 handset OEM and is already in use with CEVA customers and partners.
The CEVA-XC SDK enables the full implementation of the physical layer (PHY) signal processing in software for a range of communication standards, including LTE, LTE-Advanced, HSPA+, HSPA, TD-SCDMA, WiFi, DTV demodulation, digital radio, and GPS. The SDK is comprised of the CEVA-XC323 silicon, including CEVA’s innovative Power Scaling Unit (PSU) which enables advanced power management within the SoC, a comprehensive set of optimized DSP software libraries, and a broad range of standard interfaces, enabling easy integration into customer-specific system designs. The kit also includes complete debug, profiling and tracing capabilities in real-time, to enable the modeling of real system conditions well in advance of customer silicon being available. The development kit is supported by CEVA-Toolbox, a complete software development, debug, and optimisation environment.
“Our CEVA-XC silicon-based software development kit will significantly accelerate software-defined modem design and development by our customers and partners and enables the full validation of their designs in real-time before taping-out their silicon,” said Eran Briman, vice president of marketing at CEVA. According to Briman, “This will fundamentally reduce the cost, risk and design efforts associated with supporting still-evolving standards and bringing multi-mode communication designs to production silicon for our customers.”
The development kit includes: 6.5Gbps optical transceiver, dual port 1Gbps Ethernet, 1GB of DDR2 memories, 64MB SSRAM memories, HDMI in/out ports, dual Serial Rapid IO transceivers, and multiple large FPGA modules open for user programmability to add SoC specific logic. The CEVA-XC323 silicon was manufactured in a 65nm process and includes the CEVA-XC323 DSP, Power Scaling Unit (PSU), two XC-DMA controllers, program cache, 512 KB L1 data and 1MB shared L2 memory, external 64/128-bit AXI master and slave interfaces, 32-bit master APB interface, multiple efficient master/slave memory interfaces, Power Management Unit (PMU), Timers, Interrupt Control Unit (ICU), GPIOs, and more.