Renesas Electronics, a premier supplier of advanced semiconductor solutions, has announced the availability of a network search engine (NSE) system-on-chip (SoC) reference design that eliminates the development time for search offload engine in the communication industry’s fastest-speed class 400-gigabit per second (Gbps) network equipment. Targeting router and switch applications, the reference design comprises a network search engine evaluation board and a Xilinx field-programmable gate array (FPGA) employing a search SoC control IP to simplify the integration of custom functions. Traditional 400 Gbps network processing systems consist of dedicated SoCs such as ASICs or network processors. By using this reference design, system manufacturers can quickly deploy 400 Gbps systems with substantially improved performance for routing and switching applications such as video traffic at endpoints.
The reference design not only provides design data on an evaluation board populated with the R8A20686BG, a Renesas NSE SoC capable of up to two billion packet search operations per second, but also includes the newly developed search SoC control IP and control software that would otherwise require a substantial amount of time to develop.
Faced with the challenges of increasing numbers of IoT terminals and the migration to cloud computing, service providers are focused on widespread adoption of 400 Gbps class equipment. At the same time, the diversification of endpoint applications to accommodate varying network traffic loads on an on-demand basis requires an efficient network environment that is scalable and flexible. Renesas’ NSE SoC reference design combines high-speed packet search with the flexibility of SDNet packet processing technology from Xilinx, Inc., ensuring the design will be able to grow with the ever-changing network.
“Thanks to the close relationship with Renesas, both companies have been able to bring best of breed technology to solve customer challenges and deliver complete solutions for hardware, software, and IP,” said Gilles Garcia, director of communications business at Xilinx. “Accelerating time to revenue is critical and the joint reference design is clearly driving this objective.”
Key features of the NSE reference design:
1) Reference design shortens the development timeframe of 400 Gbps communication systems
The new reference design includes:
• A VCU110 evaluation board populated with a Xilinx Virtex Ultrascale XCVU190-2FLGC2104E FPGA
• A daughterboard populated with the Renesas NSE SoC that is connected directly to the Xilinx VCU110 via FMC connectors
• System-level reference design data integrating the NSE SoC and Xilinx’s SDNet technology
• Search SoC control IP and control software suite
For system manufacturers, the reference design eliminates the time-consuming process of search offload engine controller development. By integrating Xilinx’s programmable SDNet data plane hardware and NSE controller, this network processing solution is able to accelerate development time in the order of months.
2) High-performance with up to two billion operations per second, for the realization of 400 Gbps network systems
The tightly integrated packet processing reference design is optimized for multi-thread requests. By providing up to eight internal search request ports, this solution is able to process multiple requests in parallel, which fully utilizes the available bandwidth and extracts the maximum performance of the NSE SoC. The result is a scalable solution capable of supporting 400 Gbps-class network systems with tables of up to one million entries running at up to two billion searches per second. This simplifies the task of configuring, for example, search operations utilizing multiple Ethernet ports each operating at over 100 Gbps, or multiple search operations using pipeline packet processing, to achieve communication speeds at the 400 Gbps level.
3) Control software suite supports multiple applications and flexible reconfiguration without prior hardware knowledge
The control software, developed in conjunction with the reference design, allows system manufacturers to easily configure up to 32 independent search tables. System management tasks, including table configuration and maintenance, are done entirely through software with minimum hardware knowledge requirements. Moreover, all management tasks can be performed in real time during live traffic with no interruption, making it possible for reconfiguration post deployment. Applications such as load balancing in a software-defined network (SDN) environment or software-defined infrastructure (SDI) will be able to take advantage of this programmability feature.
In addition to this 400 Gbps solution, Renesas offers a 200 Gbps design with the same NSE SoC as well as a low-power 100 Gbps solution utilising LLDRAM-III memory and an FPGA. Renesas’ wide range of search offerings allows system manufacturers to select a solution that best meets their specific requirements and is able to scale with the rapid advancement in network technologies.
For details on the Renesas S series network search engine, visit: https://www.renesas.com/en-hq /products/memory/network-search-engine.html.