New verification debugger offers significant productivity improvements

The Incisive Debug Analyzer from Cadence Design Systems is a new verification debug product for RTL, testbench and SoC verification that offers significant reductions in debug time and effort. According to Cadence customers who have used this unique, multi-language debug solution have reported average time savings of up to 40 percent or more.

“Incisive Debug Analyzer has helped us fix bugs in minutes that previously would have taken hours to debug, including the root cause of complex multithreaded behaviours in our HDL design and, more importantly, in the verification environment,” said Eli Zyss, vice president of Silicon Design at Altair Semiconductor.

With many SoC companies now spending over 50 percent of their overall verification effort in debug, Incisive Debug Analyzer targets this verification bottleneck with a range of new and unique debug features. For instance, the debugger allows users to step forward or backward through their hardware verification language (HVL) and hardware description language (HDL). Additionally, users can click directly on a line or variable to jump forward or backward through time to the point when the source code line was executed or a variable value changed, allowing them to pinpoint the bug(s).

Other features include integrated, interactive log file analysis capabilities with smart filtering and clickable messages that take users directly to the point of interest in either the source code or the waveform database. The debugger provides relevant debug investigation information that allows users to quickly and easily filter messages coming from any platform (HVL and HDL code) and explore the cause of the messages by providing causality relations and debugging leads.

www.cadence.com

 

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