Microsemi has expanded its Synchronous Ethernet (SyncE) product portfolio with a single-chip, ZL30162 timing card device designed for mobile infrastructure and packet-based carrier Ethernet networks. The ZL30162 features four T0 high quality and highly programmable integrated digital phase lock loops (DPLLs), capable of locking up to 11 inputs for applications that require independent transmit and receive timing paths.
The company has also introduced the ZL30161 and ZL30163 timing card devices with single and dual DPLLs, respectively. Each of the DPLLs on the ZL30161, ZL30162 and ZL30163 can be configured to perform as numerically controlled oscillators (NCOs) to recover a clock based on packet-based timing protocols such as IEEE1588 that can be used for GSM, WCDMA and LTE applications.
The ZL30162 is based on the company’s two stage ClockCenter architecture and supports any rate-to-any rate frequency translation from 1Hz to 750MHz, including GPS 1 pulse per second (pps) input. As a monolithic device, the ZL30162 allows for very flexible input reference switching and output clock configuration with very low power consumption. The four high-precision synthesizers generate output clock frequencies with jitter performance that can directly drive 10G and 40G PHY devices.
With this capability Microsemi is able to capitalise on growing opportunities for 10 Gigabit Ethernet devices in Carrier Ethernet applications. In a recent report, Infonetics Research noted that Carrier Ethernet equipment ports will top 95 million worldwide by 2017, with 10 Gigabit Ethernet growing fast to pass 1 Gigabit Ethernet.
“Our highly integrated ZL30162 allows equipment makers to use a single device to meet the requirements of both timing card and line card applications,” said Maamoun Seido, vice president of Microsemi’s Timing Products group. “In addition, this highly integrated device complies with ITU-T Recommendation G.8262 network synchronization performance guidelines, which makes it ideal for a wide range of applications such as wireless base stations, radio network controllers, gateways, aggregation and transmission equipment, and routers while reducing design complexity.”
The ZL30161 features one DPLL and three synthesizers, which is ideal for use in wireless base stations where multiple different frequency clocks are required by baseband processor. The ZL30161 can take any clock from 1Hz to 750MHz and generate up to six LVPECL and six LVCMOS clock outputs. The ZL30163 features two DPLLs and four synthesizers ideal for traditional active and redundant timing card applications or in “single board system” applications where the timing device provides both timing card and line card functionality.
All three devices support narrow loop bandwidth (0.1 mHz to 1 KHz), holdover, hitless reference switching and compliant to different ITU-Recommendations related to network synchronization. Any input reference can be fed with Sync (frame pulse) or clock and each of the DPLLs can be programmed to synchronize to sync pulse and sync pulse/clock pair.