Microsemi Corporation is making available six new multi-frequency, ‘any-rate’ clock synthesis and frequency-conversion/jitter-attenuation products. These solutions focus on high frequency and ultra-low jitter output clocks with integration of fan-out buffers and optional custom configuration. These solutions target applications such as enterprise routers and switches, storage area network (SAN) equipment, servers and communications equipment.
With the increase of data rates and bandwidth demand to support faster access to data, high-speed transceivers are deployed in new systems to meet these requirements. Microsemi’s new clock generator family is ideal for clocking high-speed transceivers, including 10G, 40G and 100G Ethernet, and supporting many interfaces including Fiber Channel, Infiniband, XAUI and PCI Express.
The MAX24405/10 and MAX24505/10 high-performance clock synthesizers and the MAX24605 and MAX24610 high-performance jitter attenuators are able to deliver jitter as low as 180 femtoseconds to provide spec-compliant timing for high-performance system components and multi-gigabit interfaces. All variants provide any-to-any frequency conversions for clock signals from 10MHz to 750MHz.
Market research firm Databeans estimates the clock generation integrated circuit market is likely to grow from more than $700 million in 2012 to approximately $1 billion in 2017.
Each product variant integrates two synthesizers and supports two independent frequency families, replacing competing two-chip solutions. The MAX24505 and MAX24510 have on-chip EEPROM for custom configuration allowing designers to easily provide desired clocks immediately after power-up.
Additional features include: the ability to generate up to 20 output clock signals in two frequency families with control over each output clock’s signal format, voltage, drive strength, frequency divider and phase, eliminating the need for external support components such as fanout buffers and format converters; the MAX24605/10 jitter attenuators integrate a low-loop-bandwidth digital phase locked loop (DPLL) to filter low-frequency jitter starting at 4Hz; and all variants are pin-compatible providing easy migration of clock-tree designs from one platform to another.