Microsemi’s Ted Speers joins inaugural RISC-V Foundation board of directors to support company’s IoT growth using new emerging ISA standard

Microsemi Corporation has announced that Ted Speers, head of product architecture and planning for its system-on-chip (SoC) business unit, has been appointed to the inaugural board of directors of the RISC-V Foundation. The nonprofit formally introduced Speers and six other board members at the fourth annual RISC-V Workshop, held at MIT in Cambridge, Massachusetts July 12-13, 2016.


RISC-V (pronounced “risk-five”) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, and is now set to become a standard open architecture under the governance of the RISC-V Foundation. RISC-V is designed to be scalable for a wide variety of applications, easy to implement with regard to size and power, and offered under a permissive Berkeley Software Distribution (BSD) open source license. Under the leadership of Speers and his fellow board members, the foundation is working to ensure the ISA becomes the industry standard for all computing devices, which will support continued growth of Internet of Things (IoT) applications.


“RISC-V’s new ISA was designed initially to support computer architecture research and education, and has now found many more uses in the real world. Our goal is to provide a free and open clean-slate designed ISA that is simple, yet supports extensibility and specialisation,” said David A. Patterson, Pardee professor of computer science at UC Berkeley, where the RISC-V ISA was developed. “We are excited to see leading semiconductor companies using RISC-V to offer highly differentiated solutions to emerging markets.”


Through Microsemi’s early involvement in the creation of the RISC-V Foundation, Microsemi has an established leadership role in the emerging standard and ecosystem. Evidence of that involvement was on display at the July 13 RISC-V Workshop, where Microsemi collaborated with other companies in a “Hands-On RISC-V Tutorial Session.”


“When we first came across RISC-V, we knew it was going to be a great fit as a compelling soft processor solution for Microsemi’s low power, reliable, secure FPGA roadmap,” said Speers. “The vision of the team behind RISC-V, which includes some of the most respected computer architects in the world, was compelling. We also saw RISC-V as a great fit for implementing clean-slate processor capabilities for security, trust and reliability that are not only central to Microsemi’s industrial and defense markets, but will be central to the emerging IoT market. With the early support of companies including Google, IBM, HP and NVIDIA, in addition to Microsemi, it is now evident there is strong disruptive potential for RISC-V in the rapidly evolving data center market.”



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