Mentor Graphics” solutions have been validated by TSMC with a true 3D stacking test vehicle for TSMC’s 3D-IC Reference Flow. The flow expands support from silicon interposer offerings to include TSV-based, stacked die designs. Specific Mentor offerings include capabilities for metal routing and bump implementation, multi-chip physical verification and connectivity checking, chip interface and TSV parasitics extraction, thermal simulation, and comprehensive pre- and post-package testing.
The Mentor Graphics 3D-IC flow for TSMC provides a number of enhancements across the Mentor IC product portfolio. The Olympus-SoC place and route system serves as the 3D-IC physical design cockpit for both silicon interposer- and TSV-based designs with support for cross-die bump mapping and checking; TSV, microbump, and backside metal routing; and copper pillar bump implementations.
The Pyxis IC Station custom layout product provides schematic-driven layout that supports a TSV design flow. It also enables both orthogonal and 45 degree redistribution layer (RDL) routing. Specific enhancements for the TSMC 3D-IC flow include improvements to the bump file import process.
Whether the designer is working in a custom or digital design cockpit, both the Calibre nmDRC and Calibre nmLVS products provide inter-die design rule and layout vs. schematic checking, including IO alignment accuracy verification, and connectivity checking for double-sided bumps using either DEF or GDS input. The Calibre xRC and Calibre xACT products extract parasitics for backside routing and single- or double-sided bumps defined in DEF or GDS formats. They also handle TSV-to-TSV coupling extraction to drive static timing analysis and SPICE simulations, and generate TSV sub-circuit equivalents for multi-die parasitic models.
In the test area, the Mentor Tessent MemoryBIST product supports testing of stacked Wide IO DRAM die, while Tessent TestKompress provides die-to-stack level test pattern translations for both compressed and uncompressed test patterns. Tessent IJTAG also supports 3D interconnect tests for dies wrapped with IEEE 1149.1 and 1500 style wrappers.
To address the thermal issues inherent in 3D-IC designs, the Mentor FloTHERM product provides both static and transient thermal models for dies and 3D assemblies, and works with the Calibre RVE and Calibre DESIGNrev products to provide die and package level temperature visualizations.
“Deep collaboration with Mentor in 3D-IC has resulted in a comprehensive solution for our mutual customers,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Extending Mentor products to cover true 3D stacking gives our customers flexibility to choose among different scaling alternatives, and a smooth transition between approaches.”
“It paves the way for our customers to access 3D-IC technology with comprehensive support of a full 3D-IC flow from physical design through thermal analysis, verification, extraction, and test without major disruption to their existing development process,” said Joseph Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor Graphics. “The designer’s approach to scaling can remain focused on performance and cost targets, without the risk of unfamiliar methods and tools.”