Low jitter fully sync -compliant clock device unveiled by Silicon Labs

Silicon Labs has unveiled what it claims is the industry’s lowest jitter, lowest power and most frequency-flexible timing solution for high-speed networking equipment based on the Synchronous Ethernet (SyncE) standard. Offering a combination of any-frequency synthesis and jitter performance (as low as 263 femtoseconds RMS), the new Si5328 precision clock multiplier and jitter attenuator addresses the need for ultra-low jitter physical layer reference clocks in Carrier Ethernet switches and routers.

As the telecom infrastructure market is transitioning from legacy SONET/SDH networks to higher-speed, more cost-effective Ethernet networks, a key enabling technology behind this transition is Synchronous Ethernet, which is used to distribute accurate timing in Gigabit Ethernet (GbE), 10 GbE, 40 GbE, and 100 GbE Carrier Ethernet switches and routers. Every Carrier Ethernet switch and router requires a high-performance SyncE clock to provide wander filtering, distribute timing and provide a low-jitter Ethernet PHY reference clock.

The Si5328 looks to address this market and is fully compliant with ITU-T G.8262 SyncE clock requirements including EEC Options 1 and 2. When paired with a Stratum 3 temperature-compensated crystal oscillator (TCXO), the Si5328 meets all of the jitter, wander and holdover requirements specified by the SyncE standard. With its integrated loop filter featuring selectable loop bandwidths (0.1 Hz and 1 to 10 Hz), the Si5328 can be designed into any networking system that must comply with SyncE specifications. This integration eliminates the need for expensive discrete timing card phase-locked loops (PLLs) in some systems and provides manufacturers the assurance that their networking products can be deployed worldwide by their end customers.

The Si5328 SyncE clock can generate any output frequency ranging from 8 kHz to 808 MHz and from any input frequency from 8 kHz to 710 MHz. This frequency-flexible any-rate capability enables networking system designers to synchronize to and generate virtually any legacy telecom or SyncE frequency, simplifying system designs from GbE to 100 GbE. The Si5328 can be digitally reconfigured through I2C or SPI interfaces without the need for costly bill of materials (BOM) changes.

The Si5328 clock’s high level of single-chip integration greatly simplifies printed circuit board (PCB) design and its DSPLL architecture eliminates the need for external crystal and loop filter components, reducing PCB area while also maximizing immunity to board-level noise. Selectable output signal formats (LVPECL, LVDS, CML and CMOS) ease interfacing with popular Ethernet transceivers and eliminate expensive level shifters and other filtering components. Powered by a single 2.5 or 3.3 V supply, the Si5328 operates without the need for multiple power supplies and discrete filtering required by competing SyncE timing solutions.



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