Low cost image sensor extender reference design from Lattice

Lattice Semiconductor has unveiled the SensorExtender reference design that is able to offer a low-cost approach to remotely locate image sensors up to eight meters away from the image signal processor (ISP) and transmit and receive video signals at resolutions that range up to 720p60 and 1080p30.

The reference design uses inexpensive low-cost Cat5E cable to carry high-definition video and to send I2C sensor control signals from the ISP during the vertical blanking period. Three twisted pairs carry the video and commands while a fourth pair provides power and ground to the remotely located sensors.

This solution serves applications that require image sensors to be separated from the image signal processor, which are often placed in tight spaces without room for adjacent ISPs to process the image. Typical applications include medical probes, large screen TVs with an integrated HD camera, surveillance domes, piping inspection ports, and point-of-sale scanners. The SensorExtender may link a single sensor to an ISP or connect a number of sensors to a central processor.

“Many customers and partners wanted a low-cost digital solution to put image sensors in difficult-to-reach places far from the ISP as well as benefit from the clarity and quality of HD images,” said Ted Marena, Director of Solutions Marketing at Lattice Semiconductor. “The combination of our video expertise and the flexibility of our low- cost FPGAs enables camera system designers to easily and inexpensively implement this compelling solution.”

The reference design uses two Lattice MachXO2 low density FPGAs: one is placed next to the image sensor and the other is located just before the ISP. A single twisted pair CAT5E/6 cable connects the two.

The design offers a variety of interfaces (before serialization) for CSI-2, HiSPi, parallel, or sub-LVDS image sensors along with support for extending two or more image sensors. Additionally, the reference design allows parallel or serial ISP interfaces (after-deserialization). Designers can configure parallel interfaces to handle 1.8V, 2.5V, or 3.3V LVCMOS levels.

The reference design is tested with the Aptina MT MT9M024 and the Lattice HDR-60 camera development kit’s base board.



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