Learn to design CPLDs and FPGAs “@MachX02 Speed” with Lattice Semiconductor

MSC Gleichmann is hosting a Lattice Semiconductor “@MachX02 Speed” seminar at the Imperial War Museum, Duxford, Cambridgeshire on 21 November 2012. With a focus on the MachX02 family of non-volatile, infinitely reconfigurable, Programmable Logic Devices (PLDs), this training event will address all aspects of hardware and software design, looking at the product line’s unique features and the development tools, reference designs and other support that is available from Lattice and MSC.

Adrian Elms, Business Development Director at MSC Gleichmann said, “Although primarily targeted at design engineers, this seminar will be of value to R&D managers, decision makers and engineers who want to understand how this technology can accelerate system development. It also provides delegates with an opportunity to meet and network with representatives from Lattice.” He also commented, “These events are incredibly popular, so we have to allocate places on a first come, first served basis.”

The seminar runs from 10am to 4pm and costs £49.99, which includes a buffet lunch, a USB memory stick containing all the presentation material, user guides and reference designs plus a hardware development kit. Further details of the event and how to register can be obtained from Jo Seymour or from MSC Gleichmann’s website:

E-Mail: jsey@msc-ge.com

Phone: 01932 268990



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