CIE Components in Electronics
The ISLA224S/ISLA214S50 series represent the first ADCs now in production with JESD204B serial outputs. The integrated JESD204B-compatible transmitter offers data rates up to 4.375Gbps per lane, requiring only two lanes to support either the dual channel 14-bit 250Msps converter (one lane per channel) or the single channel 14-bit 500Msps device. An optional third lane is included in the transmitter to support the maximum sampling rate while operating the serial lanes at less than 3.125Gbps, providing backwards compatibility with the JESD204A standard to support lower cost FPGAs.
The JESD204B transmitter also provides deterministic latency between the ADC sample clock and the serialized data stream. This meets the synchronization requirements of multi-channel and I/Q communications systems.
Power consumption for the ISLA224S25 is just 980mW at 250Msps, compared with 1000mW or higher among competitive serial devices with lower sample rates. For the ISLA214S50, power consumption is just 1050mW compared with 2500mW for competing products.
The ADCs feature a compact footprint of just 7 mm x 7 mm and are built using Intersil’s FemtoCharge technology on a standard CMOS process with the proven core from Intersil’s popular ISLA224Pxx series, which delivers best-in-class signal-to-noise ratio (SNR).
The ISLA224S and ISLA214S50 are optimal for high performance data acquisition and broadband communications systems. They are also ideal design choices for high speed medical imaging systems, microwave receivers and radar or satellite antenna array processing, and other high speed applications. Also, the integrated 8b/10b serializer eliminates the need for an external serializing device, simplifying the design of serial-data communications systems.
Intersil is offering an evaluation kit for use with these new ADCs that includes a modular hardware design, including a proprietary motherboard and interchangeable daughter cards, and Java-based software. The motherboard’s FPGA is available as a reference design for a SERDES receiver, and the daughter cards are compliant with the VITA 57 FPGA Mezzanine Card (FMC) standard, allowing it to also operate with FMC host cards such as the ML-605 from Xilinx.
