Imperas updates Free reference model riscvOVPsimPlus with new RISC-V P (SIMD/DSP) extension and Architectural Validation Test Suites

Imperas Software Ltd. announces the latest updates to riscvOVPsimPlus with support for the near ratified P extension and architectural validation test suites.

The P (or Packed SIMD/DSP) extension is a significant addition to the flexibility of the modular RISC-V ISA (Instruction Set Architecture); it supports real-time data processing applications as part of the main processor pipeline without the need for the associated inefficiencies of a co-processor. For processor hardware verification, a basic test suite helps ensure implementations have a basic software level compatibility to the new P extension as a reference to the developers’ interpretation of the written specification.

riscvOVPsimPlus is a popular free ISS (Instruction Set Simulator) that is an envelope model that can be configured to cover all of the ratified RISC-V specifications and standard extensions. Also included are several Architectural Validation Test Suites, which form a basic test plan for software level compatibility within the specification definitions. The Imperas models are available as open-source and licensed under the Apache 2.0 flexible open-source license. All models, virtual platforms and example models are provided to the community via the Open Virtual Platforms website www.OVPworld.org. The Imperas commercial simulation technology and products are based on the freely available open-standard public OVP APIs.

The Imperas RISC-V architectural validation test suites are collections of tests focused on specific ISA extensions that provide basic testing of instruction execution and usage of the full range of operands with a set of representative data values. They are not a substitute for full detailed tests suites for design verification but provide detailed coverage reports of the different parts of the architectural specification tested. The currently released test suites available free on the OVP website now include P SIMD/DSP, K-crypto, V-vector, B-bitmanip, F, D, I, M, and C.

“Flexibility within a framework of compatibility is the essential foundation of the RISC-V ISA,” said Chuanhua Chang, Andes Technology Corporation, Chair of RISC-V International P Extension Task Group. “The RISC-V P extension defines a rich set of integer SIMD/DSP instructions operating on existing integer registers to support complex data processing within the constraints of real-time applications. However, the hardware specification is just the start – adoption and success depend on the software ecosystem, which is supported with the reference models and test suites from Imperas.”

“By combining SIMD/DSP functionality within the RISC-V ISA offers the ideal balance for performance, flexibility and efficiency,” said Wei Wu, PLCT Lab, ISCAS, Vice-Chair of RISC-V International P Extension Task Group. “The Imperas RISC-V reference model provides the ideal starting point to explore and develop software algorithms based on the new RISC-V P extension.”

“The Imperas simulation technology and RISC-V reference models are in active use in some of the most complex RISC-V verification projects,” said Simon Davidmann, CEO at Imperas Software Ltd. “RISC-V is changing the design process as new design exploration can start without many of the traditional barriers. The adoption of riscvOVPsimPlus with the new RISC-V P extension support helps provide clarification of the specification boundary as a useful guideline for innovation in new processor designs.”

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