Hardware and software engineers designing SoC FPGAs stand to profit from Aldec QEMU Bridge

Aldec, Inc., an industry leader in Electronic Design Verification, has added QEMU Bridge to the latest release of Riviera-PROTM, the company’s advanced verification platform, to enable hardware/software co-simulation of designs intended to run on SoC FPGAs.

Integration and simulation of FPGA custom IPs with software applications and drivers executing on the virtual processor in QEMU is now possible and simplified. The QEMU Bridge converts SystemC TLM transactions to AXI and vice versa providing a fast interface for co-simulation.

“System integration is becoming increasingly challenging in light of growing design sizes and device complexity,” Radek Nawrot, software product manager. “The co-simulation activities facilitated through QEMU Bridge enable hardware and software engineers to work together to locate, identify, and retire bugs at an earlier stage in the development cycle, thus saving both development time and costs.”

Hardware engineers (using Riviera-PRO) can set break points in the HDL, examine data flow, and even analyse the code coverage and paths that are exercised by the software application running in QEMU.

Software engineers (using QEMU) can use GNU Debugger (GDB) to instrument both the kernel and the driver to step through the code using breakpoints.

Also new to Riviera-PRO 2017.10:

  • Significantly improved performance when using code containing many inline randomised calls
  • Simulation speed of UVM design is up to 29 per cent faster
  • VHPI design simulation speedup
  • Direct interface with ALINT-PROTM Design Rule Checking tool
  • Mixed-Signal Silvaco SmartSpiceTM Interface (initial stage)
  • Pre-compiled Aldec AXI BFM 1.7
  • Histogram can now be created in the Plot window


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