Ericsson has unveiled the latest version of its DC/DC Digital Power Designer software tool, which includes a number of new features that enable board power designers and system architects to simulate either simple or complex power schemes, reducing time-to-implementation and time-to-market. The Ericsson Power Designer (version 1.4) features advanced loop compensation functionality that makes it easier to simulate output capacitors and filter networks such as PI filters on the output of 3E Point-Of-Load (POL) DC/DC converters, and to optimise loop response without hardware modification for the end application.
Commenting Patrick Le Fèvre, Marketing and Communication Director, Ericsson Power Modules, said: “The Ericsson Power Designer software has been developed in close cooperation between board-power designers and power-systems architects to deliver an advanced tool that unlocks the high level of flexibility offered by digital power architectures. Including simulation and improved visualization, version 1.4 reflects our commitment to our customers to deliver the most efficient tools and solutions that contribute to energy optimization and reducing time-to-market.”
Using the tool’s Loop Compensator, it is possible to enter values provided by system designers to optimise loop response to match specific profiles such as that required by fast transient conditions, which are often seen when powering processors that are switching from low to high traffic load. The Loop Compensator tool is based on mathematical algorithms using switched-Hamiltonian differential-equation models, adding in the results from simulation, all presented through an intuitive graphic user interface.
The Loop Compensator includes: PID control optimisation, capacitance optimisation and load transient response, in addition to the ability to enter values for the power module and load capacitor, as well as the inductor to simulate a PI filter.
Silicon process geometry is now reaching the 20-nanometer node with processors increasingly requiring ultra-low voltages of 1V and below, with the consequence that some processors will draw currents in excess of 100A. In addition to this, to efficiently power these new demanding components, new power architectures based upon multiple POL converters that distribute energy to multiple points will require a move from three to six modules in parallel, with the accompanying risk of high-current interference and disturbance. Ericsson’s 3E digital POL converters are designed for these types of applications and are able to provide efficient current sharing, phase spreading and phase shading.
The Power Designer now includes a new tool to optimise synchronisation and phase spreading. A simulation module shows in a graphical format how the different phases are operating, the level of energy pulse from the input, and how to optimise phase spreading to lower pulse energy and to reduce input filtering, saving board space and lowering interference as a result.
The sequencing of different power sources that power a processor is highly critical. In addition to the core voltage, there are a number of auxiliary voltages that must be ON/OFF in precise order – and in an order that may vary following processor firmware update. Precise and accurate power sequencing can guarantee the highest levels of processor performance, though it requires flexibility and no hardware dependency. The sequencing tool with Ericsson Power Designer version 1.4 supports time-base and event-base sequencing. The interface includes a graphic visualization of each individual rail, which can be set in any order as required by the processor.
As a complement to the Ericsson Power Designer software, the Ericsson 3E Design Toolbox includes five boards supporting Power Interface Modules, Advanced Bus Converters, Current Sharing, Single-In-Line 3E POL regulators and a generic board accommodating through-hole 3E POL regulators. All the boards can be interconnected to reflect the end application and be configured and monitored via Ericsson Power Designer.