Multi-year licensing agreement for EnSilica’s highly-configurable, high-performance, low-power eSi-RISC processor IP covers multiple projects and architectures
EnSilica, a leading independent provider of semiconductor solutions and IP, and Solomon Systech, a leading provider of touch and display ICs and system solutions, have entered into a multi-year licensing agreement for EnSilica’s range of highly-configurable, high-performance, and low-power eSi-RISC processor IP. The multi-year licensing agreement covers the full range of EnSilica’s 16 bit and 32 bit eSi-RISC processor IP and extends the existing, successful relationship between the two companies to cover multiple projects and multiple architecture implementations.
EnSilica’s eSi-RISC processor IP has been adopted by Solomon Systech to power several of its smart touch screen controllers and drivers. Headquartered in Hong Kong with additional technology centres throughout Asia (China, Japan, Korea and Taiwan) and in Europe (United Kingdom), Solomon Systech operates on a fabless business model. The company specialises in the design, development and sales of proprietary IC products that enable a wide range of display applications for smartphones, tablets, smart TVs/monitors, notebooks and other smart devices, including wearables, healthcare devices, connected home devices, as well as industrial appliances, etc.
“With eSi-RISC already proven in several of Solomon Systech’s existing products, we are extremely pleased to be extending our relationship by entering into a multi-year licensing agreement that covers multiple projects and multiple architecture implementations,” said David Doyle, commercial director for EnSilica. “The performance, features and configurability of eSi-RISC are an ideal match for the enhanced functionality that Solomon Systech is seeking to deliver in its next generation products.”
EnSilica’s eSi-RISC is a highly configurable microprocessor architecture for embedded systems that scales across a wide range of applications. With either a 16 or 32-bit, 5-stage pipelined RISC, load-store architecture which is highly configurable and implemented in as little as 8k ASIC gates, the RISC IP core has been silicon proven in a variety of ASIC and FPGA technologies. Available in a choice of von Neumann or Harvard memory versions and using industry standard bus architecture (AMBA AXI/AHB/APB) for IP interconnection, intermixed 16 and 32-bit instructions give exceptional code density. Configurability and custom instructions deliver a solution with exceptionally low-power. eSi-RISC is implemented as a soft IP core, based on synthesisable Verilog RTL and can be easily ported to a wide range of ASIC processes and FPGAs. The design is also DFT ready, supporting full scan insertion for all flip flops and memory BIST.
Commenting further on the multi-year eSi-RISC licensing deal with Solomon Systech, Ian Lankshear, CEO of EnSilica added: “We are looking forward to eSi-RISC-based controller and driver ICs from Solomon Systech powering a new generation of display applications for smartphones, smart TVs and other smart devices.”