Engineering productivity improved through early code quality checks

Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has added a Unit Lint function to Active-HDL 10.5; where a ‘unit’ is a block of HDL code. The new feature works by running linting in the background, enabling designers to quickly perform quality checks on just the code on which they are working – without leaving their design environment. This aids productivity in the long-run, because (full) chip-level linting can then be embarked upon with increased confidence.

“Performing a Unit Lint on a block of code during the coding phase of a project greatly minimises the risk of encountering problems later in the project and helps reduce the number of design iterations that are purely correction-driven,” said Radek Nawrot, Active-HDL product manager. “Also, Unit Lint is a great way to enforce corporate coding standards early in the product lifecycle and to maintain consistency across the team.”

Unit Lint checks include: the identification (and an indication of the sensitivity) of incomplete and/or redundant combinational and sequential process logic; the identification of incomplete and/or redundant condition statements and unintended latches; confirmation of FSM coding correctness (including the detection of simple cases with dead and unreachable states); basic X propagation checks; the identification of data conversion coding errors (that can lead to sign and bit-width mistakes); and the flagging of suboptimal synthesizable code (such as deep priority logic and arithmetic resource sharing).

Active-HDL is a Windows-based, integrated FPGA design creation and simulation solution for team-based environments. The Unit Lint function runs Aldec’s ALINT-PRO in the background; provided the user has either the Expert edition of Active-HDL or a standalone license for the linter.

The full linting tool can also be launched from within Active-HDL, for chip-level linting where checks would typically include verifying clock and reset trees, checking for Clock and Reset Domain Crossings (CDC and RDC respectively) and evaluating the design’s testability.

The Active-HDL 10.5 release includes numerous new features, usability enhancements, and performance optimisations.

For additional information, tutorials, free evaluation download and a What’s New Presentation, visit www.aldec.com/en/products/fpga_simulation/active-hdl.

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