Digital power innovations overcome data centre thermal challenges

Heat generated during power conversion, particularly in power supplies over 100W, is one of the greatest challenges facing data centre and telecom network facilities. As wasted energy, this heat not only represents financial loss but also imposes further unwanted cooling costs to ensure the safe removal of waste heat and improved system reliability. In this article, Jian Yin, Intersil Corporation, talks about new power modules enabled with packaging technologies that generate less heat under all operating conditions, and provide efficient thermal dissipation which can effectively address both aspects of this issue

 

Wasted heat is one of a number of issues that power-supply designers must deal with. The latest generations of on-board microprocessors and FPGAs demand increased peak current, fast load transient response, and multiple supply rails including a core voltage of 1.0V or less. This dictates the close placement of point-of-load (POL) converters that can deliver a fast dynamic response without needing large numbers of decoupling capacitors that otherwise consume precious board real-estate.

Digital power conversion can enhance energy efficiency, but not all modules on the market today take full advantage of digital techniques to maximise transient performance. In addition, improvements in package technology and internal component positioning are needed to minimise reliance on bulky and expensive heatsinks.

 

Maximising digital power advantages

Compared to conventional analog designs, digital power converters can operate at high efficiency across a wider range of load conditions by taking advantage of adaptable features such as dynamic voltage scaling and frequency shifting. 

 

Implementing the PWM, loop control and feedback digitally offers the advantages of maintaining stability without suffering the lack of responsiveness typically experienced with analog control. This allows the output capacitance required for handling transient load events to be significantly reduced, saving board real estate and bill of material costs.

 

Although digital control offers advantages in the fast loop design, many manufacturers are not taking full advantage of what the technology offers and have simply implemented the core analog PWM techniques in digital form. Digital control makes it possible to build far more flexible control loops by incorporating n x FSW (switching frequency) oversampling, multi-rate sampling, various types of digital filters for notching and phase shaping, and Fourier transform. These features associated with complex digital signal processing are often not feasible with traditional analog control techniques.

Figure 1 compares the control blocks for Type III analog compensation typically used by voltage-mode controlled buck converters in the market today, against a digital architecture optimised for fast response.

 

Typically, the core of a Type III compensator is a transfer function with two zeros and three poles. The first pole near origin forms a high gain at low frequency for steady state regulation, while the second pole compensates the output capacitor ESR zero. The third pole increases attenuation of the high-frequency noises caused by switching ripples. Meanwhile, the two zeroes are used to shape the loop gain at crossover and boost phase to make the loop stable. Figure 1a shows the third pole separating from the rest of the Type III compensator. 

 

The one-pole low pass filter removes the switching ripple noises from the PWM modulator to maintain stability. However, on the other side, it inevitably introduces extra phase lag to the loop, limiting the loop bandwidth and response speed in order to have sufficient phase margin. The only way to achieve further improvement with this analog architecture is to employ variable-frequency switching techniques, using higher frequency when the voltage is changing rapidly. This can be undesirable in systems that require tight control of the noise spectrum to ensure electromagnetic compatibility (EMC).

In the digital fast-response control loop shown in figure 1b, the ADC is over sampling at a frequency of n x Fsw, where n > 1. Therefore, the phase lag or group delay introduced by the analog-to-digital conversion is negligible for the loop stability. Because of the over sampling, it is feasible to design the core compensator Gc(z-1) to have a similar frequency response to the two-zero two-pole compensator in Figure 1a, in terms of loop gain and phase. But most importantly, the filter employed to attenuate the high frequency switching ripple noises can be designed uniquely by digital means and completely differentiated from the analog compensator’s single-pole low-pass filter in Figure 1a. 

 

Benefiting from the advantages of digital signal processing, a low-latency FIR ripple filter can be easily incorporated to reject all repetitive ripple elements. All that remains are the non-periodic elements in the waveform, including transient steps with little or no delay. This results in more than 20dB of ripple reduction without a significant time delay, thus allowing higher gains and higher bandwidths. Load transient performance is significantly improved.

 

Figures 2a and 2b illustrate the effects of Intersil’s fast digital compensation on transient performance by comparing the ISL8273M digital POL converter with a competitor’s 26A module with similar output capacitance and operating conditions. With load current slew rate at >200A/µs, the ISL8273M keeps peak-to-peak deviation within 100mV and recover time at 22µS. The competing module has a much larger deviation of 165mV and recover time of 55µS with only 20A/µs current slew rate.

Tackling thermal management

Digital power has demonstrated greater efficiency and improved stability in the presence of load transients, while saving external components such as capacitors. However, the high current demands of the latest processors and FPGAs challenge the thermal performance of traditional power module package technologies. Land Grid Array (LGA) power modules typically have a dual-layer printed circuit board that carries the semiconductor die and other components, and interconnects them. 

 

Advantages of this type of construction include good routing capabilities and straightforward electrical interconnections, but junction-to-case thermal resistance can be relatively poor. On the other hand, QFN (Quad Flat No-leads) modules have a metal lead fame that ensures very good thermal conductivity at the expense of limited routing capability. Modifying the QFN to improve routing tends to increase the package cost.

 

The High Density lead-frame Array (HDA) is an alternative package type that delivers high thermal conductivity as well as adequate routing capability. The HDA has a single-layer substrate comprising a peripheral portion that includes surface-mount pads for attachment to the main board, and an interior portion with floating contact pads that are coupled to internal components and electrically isolated from the peripheral contact pads. This arrangement of peripheral and interior contact pads endows HDA power modules with PCB trace routing capabilities comparable to those of a dual-layered PCB while the substrate, with its single metal layer, ensures excellent thermal conductivity to maximise heat dissipation.

 

3D package innovation

Intersil has achieved a further significant advance in the thermal performance of power modules by optimising the design of the inductor, which is a critical piece of the electrical-mechanical system. The inductor must be physically large to achieve low DC resistance (DCR), and thereby minimise copper and core losses, while maintaining a practical operating temperature. Unfortunately, lack of space on many telecom and datacom motherboards often forces designers to use an undersised inductor, and hence to tolerate hotspots and poor efficiency, or to add a bulky heatsink.

The 3D stackable inductor structure successfully addresses both space and efficiency constraints. The inductor is installed over the other components, as shown in figure 3, and therefore can be almost as large as the entire power module footprint. This design significantly reduces the substrate area compared to a side-by-side mounting method, while permitting a larger inductor with lower DC resistance loss and core loss. Together, the single-layer substrate and stacked inductor also enhance heat dissipation through both the top and bottom of the module.

 

Design example: 80A digital PMBus power module

The ISL8273M 80A step-down PMBus-compliant offers the industry’s highest current capacity from a compact (18mm x 23mm x 7.5mm) HDA package. Dual phases are connected in parallel to deliver current through a single output.

 

The POL has a dual-phase inductor that features a proprietary design using the 3D integration technology. Two windings are built on a single core such that the magnetic flux of the two windings are partially cancelled, thus reducing both the inductor size and core loss. Phase interleaving allows further reduction of input capacitance and output voltage ripple.

The ISL8273M can operate in harsh environments with no airflow or heat sinks. As figure 4 illustrates, it has been shown to operate with junction temperature below 80°C when supplying a continuous 80A load, at 300kHz switching frequency with 12V input and 1.0V output, mounted on a 2oz. 8-layer 4.7-inch x 4.8-inch FR4 board. The module achieves power density greater than 1055W/in3.

 

Conclusion

Efficient digital power conversion with fast loop control, and innovative 3D package technology helps system designers overcome the thermal challenges presented by the new generations of high-performance processors and FPGAs operating at low core voltages. POL digital power modules such as the ISL8273M enable a favorable combination of fast transient response, high efficiency, high power density and high reliability.

 

www.intersil.com

 

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