Synopsys has made available the first products in its new DesignWare ARC HS processor family. The 32-bit ARC HS34 and HS36 processors are the highest performance ARC processor cores developed so far, capable of delivering 1.9 DMIPS/MHz at speeds up to 2.2 GHz in typical 28 nanometer (nm) silicon.
According to the company the new HS processors have been optimised for power efficiency (DMIPS/mW) and area efficiency (DMIPS/mm2) while at the same time being able to perform high speed data and signal processing tasks. This combination makes them suitable for the embedded and deeply embedded processors within system on chips (SoCs) for products such as solid-state drives, connected appliances, automotive controllers, media players, digital TV, set-top boxes and home networking products.
When implemented in typical 28nm processes, the HS cores consume as little as 0.025mW/MHz in an area as small as 0.15mm2. The cores feature a high-speed 10-stage pipeline that supports out of order execution, minimising idle processor cycles and maximising instruction throughput. Sophisticated branch prediction and a late stage ALU improve the efficiency of instruction processing and to speed the execution of math functions, the ARC HS Processors give designers the option to implement a hardware integer divider, instructions for 64-bit multiply, multiply-accumulate (MAC), vector addition and vector subtraction, and a configurable IEEE 754-compliant floating point unit (single or double precision or both).
The ARCv2-based cores provide an 18 percent improvement in code density compared to previous generation ARC cores, reducing memory requirements. HS processors also support close coupled memory as well as instruction and data cache (HS36 only), with new 64-bit load-double/store-double and unaligned memory access capabilities that accelerate data transfers. Optional error-correcting code (ECC) hardware is available for all memories in the processor for applications that require a higher level of memory reliability and protection.
“Designing processors for high performance is simple when power and transistor budgets are not a concern. Much more difficult is designing small, efficient processors that offer enough performance for today plus additional headroom for future growth,” said Linley Gwennap, principal analyst of The Linley Group. “To optimise their ARC HS cores for embedded applications, Synopsys have taken a more streamlined approach, using fewer transistors and less power yet still delivering high throughput with an unusually flexible CPU that SoC designers can customise extensively. Its strong power efficiency and low-cost silicon footprint will appeal to many embedded-system developers.”
The highly-configurable ARC HS processors allow designers to tailor each instance of the core on their SoC balancing performance, power and area. Users can define instruction extensions to the processor pipeline that enable the integration of their own proprietary hardware accelerators.
Native ARM AMBA AXI and AHB standard interfaces are configurable for 32-bit or 64-bit transactions to optimise system throughput. SoC peripherals can also be directly accessed by the CPU in a single cycle, minimising system-level latencies and maximising hardware integration. By incorporating features to optimise the performance efficiency of both the processor and the system, the HS34 and H36 cores give designers the ability to create greater product differentiation while lowering the cost of implementation.
The new HS cores are supported by the Synopsys MetaWare Development Kit. This includes: an optimised compiler to generate highly efficient code, a debugger for maximum visibility into the software and a fast instruction set simulator (ISS) for pre-hardware software development.
“With more than 1.3 billion ARC-based chips shipping annually, we are keenly aware that each new generation of electronic devices requires processors to meet the conflicting goals of higher performance with lower power and smaller area, and that’s exactly what the ARC HS Processor Family delivers,” said John Koeter, vice president of marketing for IP and systems at Synopsys. “The ARC HS34 and HS36 cores represent a significant advancement in the ARC portfolio and demonstrate Synopsys’ commitment to extending the ARC roadmap to meet designers’ evolving embedded requirements.”