The first ChipVORX model libraries for the new generation of Arria V GX FPGA devices from Altera supporting embedded test and embedded programming are now available, according to GOEPEL. ChipVORX provides users with the opportunity to implement a so called Embedded System Access (ESA), completely omitting nail or probe contacting. In this case, per JTAG control the Altera FPGA are utilised as natural, design-integrated test centres, helping to increase test quality and to reduce effort.
“The integrated transceivers’ low power consumption has been an important feature for a number of customers on the field of communication solutions to use the new Arria V FPGA in their future designs. Our new ChipVORX models simultaneously provide support applying innovative test and programming strategies”, says Heiko Ehrenberg, Technology Officer for Embedded System Access (ESA) with GOEPEL electronic. “The ChipVORX technology’s reusability plays a particular role throughout the entire product life cycle. The FPGA embedded instruments can be utilised for prototype verification as well as production test, debugging and fault diagnosis.”
The ChipVORX models are Intellectual Properties (IP) for implementation and control of chip embedded instruments. They enable a multitude of FPGA assisted test and programming functions, among others access test of time-critical DDR-SDRAM, programming of parallel NOR and NAND-Flash, frequency measurement as well as high-speed programming of serial Boot Flash.
Within the ChipVORX framework instruments are temporarily loaded, configured and finally controlled as soft macros via the standard IEEE 1149.1 TAP into the FPGA. The entire work flow is fully automatic and synthesis-free. For all test, measurement and programming procedures there are automatic generators that are able to analyse the UUT’s functional structure and establish an interconnection from instrument to signal pin (IP to pin). Furthermore, the opportunity of interactive graphical control panels facilitates debugging.
The ChipVOR models for ArriaV FPGA were developed in close cooperation with the company and GATE alliance partner Testonica. The usage of the ChipVORX requires neither expert background knowledge nor specific FPGA tools or continuous IP adjustments. The execution of ChipVORX based routines is possible on each run-time station without further options. Also Gang applications can be implemented.
The ArriaV ChipVORX IP models are supported as standard starting from SYSTEM CASCON version 4.6.1 and are activated by the licence manager like the system software. SYSTEM CASCON is a professional JTAG/Boundary Scan development environment, developed by GOEPEL electronic with currently 47 completely integrated ISP, test, and debug tools. Regarding the hardware, ChipVORX is completely supported by the controllers of the SCANBOOSTER family, as well as by the hardware platform SCANFLEX.