CIE Components in Electronics
The CEVA-XC4000 architecture is offered in a series of six fully programmable DSP cores, which provide modem developers with a wide spectrum of performance capabilities while complying with stringent power constraints. By taking advantage of a unified development infrastructure composed of code-compatible cores, a set of optimised software libraries and a single tool chain, customers will be able to significantly reduce software development costs while leveraging their software investment in future products.
“The CEVA-XC4000 redefines the concept of a ‘universal communication architecture’, enabling every conceivable advanced cellular, connectivity, DTV, white space and powerline communication standard to be supported by a single DSP architecture,” said Gideon Wertheizer, CEO of CEVA. “Incorporating new power management techniques, we were able to dramatically reduce the power consumption for high-performance software-based processing, paving the way for modem developers to exploit the flexibility, reusability and time-to-market advantages that a software-defined approach brings.”
Addressing the ever-increasing requirement for higher performance together with lower power consumption, the CEVA-XC4000 architecture incorporates new power-oriented enhancements, including the company’s second generation Power Scaling Unit (PSU 2.0) which dynamically supports clock and voltage scaling with fine granularity within the processor, memories, buses and system resources. The architecture also utilizes Tightly Coupled Extensions (TCE) to deliver inter-connected power-optimised coprocessors and interfaces for the implementation of critical PHY functions, further reducing power consumption. A rebalanced pipeline with low-level module isolation is also highly optimized for power.
The XC4000 incorporates enhanced system-level mechanisms, queues and interfaces to deliver impressive performance, realising faster connectivity, higher bandwidth, lower latency and better PHY control. The architecture enhances modem quality by using two distinct inter-mixable high-precision instruction sets, supporting the most advanced 4×4 and 8×8 MIMO algorithms.
CEVA has also announced complete reference architectures targeting complex communication standards, including LTE-A Rel-10 and Wi-Fi 802.11ac supporting up to 1.7 Gbps. These reference architectures are complemented with highly optimised software libraries for LTE-A and Wi-Fi.
The CEVA-XC4000 DSP architecture is also supported by the CEVA-Toolbox a complete software development environment, incorporating Vec-C compiler technology for advanced vector processors, enabling the entire architecture to be programmed in C-level. An integrated simulator provides accurate and efficient verification of the entire system including the memory sub-systems. In addition, CEVA-Toolbox includes libraries, a graphical debugger, and a complete optimisation tool chain named CEVA Application Optimizer.
