CEVA looks to enrich XC DSP architecture framework

CEVA, a leading licensor of silicon intellectual property (SIP) platform solutions and DSP cores, has launched a new suite of advanced processor and multi-core technologies to further enhance the CEVA-XC DSP architecture framework for high performance wireless applications including wireless terminals, small cells, access points, metro and macro base-stations.

Among the enhancements are: comprehensive multi-core features, high-throughput vector floating-point processing and a complete set of co-processor engines offering power-efficient hardware-software partitioning. CEVA has collaborated closely with leading OEMs, wireless semiconductors and IP partners for the definition and optimisation of these technologies.

“In addition to improving performance while reducing cost and power consumption in wireless baseband designs, the new enhancements to the CEVA-XC architecture offer SoC designers a comprehensive environment to develop and optimise high-speed data flow in multi-core designs,” said J. Scott Gardner, Senior Analyst at The Linley Group. “Furthermore, the use of ARM’s latest interconnect and coherency protocols, together with advanced automated data traffic managers, as well as a dynamic scheduling software framework, position CEVA as the only DSP licensor today offering such extensive support for multi-core DSP-based SoCs.”

CEVA’s MUST is a cache-based multi-core system technology with advanced support for cache coherency, resource sharing and data management. Initially available for the CEVA-XC, MUST supports the integration of multiple CEVA-XC DSP cores in a symmetric multiprocessing or asymmetric multiprocessing system architecture, along with a broad range of technologies designed specifically for multi-core DSP processing, such as : dynamic scheduling using shared pools of tasks; hardware event based scheduling defined via software; task and data driven shared resource management; advanced memory hierarchy support with full cache coherency and advanced automated data traffic management without software intervention.

To facilitate the development of advanced multi-core SoCs containing ARM processors and multiple CEVA DSPs, CEVA has also added extensive support to the CEVA-XC architecture framework for the ARM AXI4 interconnect protocol and AMBA 4 ACE cache coherency extensions. This simplifies the software development and debugging process for SoC designs, while also reducing the software cache management overhead, processor cycles and external memory bandwidth.

The LTE-Advanced and 802.11ac standards leverage multiple input multiple output (MIMO) processing, where the system utilizes multiple antennae to transmit and receive data. In order to achieve ultra-high precision and optimal performance when processing these complex data streams, CEVA has added support for floating-point operations to the CEVA-XC vector processor unit, in addition to the traditional fixed-point capabilities. Floating-point operations are supported on full vector elements, processing up to 32 floating point operations in every core cycle to meet the performance requirements of even the most demanding wireless infrastructure applications. In addition to these enhancements, CEVA has further extended its technology leadership with a dedicated instruction set architecture (ISA) for high-dimension MIMO, including support for 802.11ac 4×4 use cases.

To further optimise advanced wireless systems for low power and performance, CEVA has introduced a comprehensive set of tightly-coupled extension (TCE) coprocessor units. These coprocessors address functions of the modem where greater performance can be achieved through the use of hardware that is tightly coupled with the CEVA-XC.

These tightly-coupled extensions are complemented by a unique automated low-latency data traffic management between the DSP memory and the coprocessors to minimise DSP intervention and enable a truly parallel co-processing capability. CEVA offers these TCEs as part of fully integrated and optimized modem reference architectures for licensees targeting user equipment, infrastructure and Wi-Fi applications, serving to lower the overall power consumption and significantly reduce customers’ development costs and time to market.

According to Eran Briman, vice president of marketing at CEVA, “The suite of technologies introduced today for the CEVA-XC will serve to vastly improve the performance, power consumption and time-to-market for multi-core DSP SoC designs targeting wireless applications. We collaborated closely with industry leaders in the handset and infrastructure markets throughout the specification process, ensuring our IP exceeds the stringent specifications required by the wireless industry.”

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