The output stream can be used to implement 3D stereoscopic video or for other multi-camera applications. The low cost of the solution enables other consumer applications such as automotive black box drive recorders and surround view cameras. The low cost, low power Lattice MachXO2 PLD and a small SDRAM chip implement the necessary logic and frame buffering that allow the two image sensors to be merged into one ISP bus.
Cliff Cheng, Senior Business Development Marketing Manager for Aptina, said, “This is the latest design in which we have collaborated with Lattice Semiconductor. Their use of the HiSPi protocol further expands the markets for our very popular HD WDR sensors that are used in smart camera and 3D depth sensing camera.”
“We are pleased to offer this dual image sensor design, which allows ISP vendors to quickly offer multiple camera solutions for the consumer market,” said Ted Marena, Director of Business Development for Lattice. “By leveraging the Aptina HiSPi (High speed Serial Pixel interface) bus of the MT9M024/MT9M034, we were able to select a smaller I/O package for the Lattice MachXO2 device, which helped lower the cost.”