CEA-Leti presenting 11 papers at IEDM 2018 & hosting workshop on disruptive technologies for data management

Leti, a technology research institute of CEA Tech, will present 11 papers at IEDM 2018 in San Francisco, Dec. 3-5, including one invited paper on scalable silicon quantum computing. It also will host a workshop covering “Disruptive Technologies for Data Management” on Sunday, Dec. 2, at the Nikko Hotel, anchored by a keynote talk from John Paul Strachan, senior researcher at HPE.

CEA-Leti’s workshop, an annual event for invited guests at the IEDM conference, begins at 5:30 p.m. Presentations include:

  • Welcome & Introduction, Emmanuel Sabonnadière, CEA-Leti CEO
  • Technologies for New Computing Paradigms, Carlo Reita, CEA-Leti
  • Enabling Heterogeneous High Performance Processors, Denis Dutoit, CEA-Leti
  • Special Key note, John Paul Strachan – HPE
  • Emerging Non-Volatile Memories for Computing, Marie-Claire Cyrille, CEA-Leti
  • Quantum Computing on Silicon : Maud Vinet, CEA-Leti

CEA-Leti’s papers at IEDM include:

Monday, Dec. 3

Session 7.2: Breakthroughs in 3D Sequential Technology

Time: 2:00 pm

Location: Continental Ballroom 5

Session 6.2: Towards Scalable Silicon Quantum Computing (invited)

Time: 2:00 pm

Location: Continental Ballroom 5

Session 7.3: Hybrid Bonding for 3D Stacked Image Sensors: Impact of Pitch Shrinkage on Interconnect Robustness

Time: 2:25 pm

Location: Continental Ballroom 6 

Tuesday, Dec. 4

Session 12.4: Very Large Scale Integration Optomechanics: A Cure for Loneliness of NEMS Resonators?
Time: 9:00 am

Continental Ballroom 1-3

Session 17.1 Characterization Methodology and Physical Compact Modeling of in-Wafer Global and

Local Variability

Time: 9:05 am

Location: Plaza B

Session 17.6: Development of X-ray Photoelectron Spectroscopy Under Bias and its Application to Determine Band-energies and Dipoles in the HKMG Stack

Time: 11:35 am

Location: Plaza B 

Session 20.3: In-depth Characterization of Resistive Memory-based Ternary Content Addressable


Time: 3:10 pm

Location: Continental Ballroom 4

Session 21.3: Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets

Time: 3:10 pm

Location: Continental Ballroom 5 

Session 18.4: Truly Innovative 28nm FDSOI Technology for Automotive Micro-Controller Applications Embedding 16MB Phase Change Memory
Time: 4:00 pm
Location:  Grand Ballroom B 

Session 20.6: In-Memory and Error-Immune Differential RRAM Implementation of Binarized Deep

Neural Networks

Time: 4:50 pm

Location: Continental Ballroom 4

Wednesday, Dec. 5

Session 37.4: Optimized Reading Window for Crossbar Arrays Thanks to Ge-Se-Sb-N-based OTS

Time: 2:50 pm

Location: Continental Ballroom 4


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