Cadence Design Systems, Inc. today announced that its full suite of Cadence digital, signoff and custom/analog IC design tools, along with advanced IC packaging design solutions, support the new TSMC Wafer-on-Wafer (WoW) stacking technology.
Support for WoW advanced packaging technology
Cadence provides flows, tools and methodologies that enable TSMC customers to manage the top-level connectivity and verification of their chip integration solutions as part of the overall design process.
- Innovus Implementation System: Supports single database top-die including front/back-side routing and backside-through-silicon-via (BTSV) support, creating connections between multiple dice
- Quantus Extraction Solution: Supports back-side routing layers, sub-circuit replacement for BTSV and die-to-die interface coupling capacitance extraction, enabling electrical analysis between the dice
- Voltus IC Power Integrity Solution: Provides die-level power map generation, enabling concurrent power analysis of multiple dice
- Tempus Timing Signoff Solution: Provides multi-die static timing analysis (STA) support, enabling a checking of timing paths that cross multiple dice
- Physical Verification System (PVS): Offers design rule checking (DRC) and layout vs. schematic (LVS) for die with BTSV, interface alignment and connectivity checks, ensuring that the two dice connect properly
- Virtuoso Platform: Includes features for bump placement and alignment on top of the existing PDK via the Virtuoso Incremental Technology Database (ITDB), creating connections between multiple dice
- OrbitIO interconnect designer: Provides interface connectivity, device flattening, port connectivity and configurable module definitions to manage top-level connectivity, enabling unified planning of die interconnect and alignment
- Sigrity PowerSI3D-EM Extraction Option: Offerselectrical modeling of the combined die and interposer, validating that the power and ground distribution is sufficient for multiple dice
- Sigrity PowerDC technology: Thermal analysis solution with interposer and die analysis capabilitiesthat allow co-simulation with Voltus IC Power Integrity Solution, enabling inclusion of temperature into concurrent electromigration analysis of multiple dice
- Sigrity XcitePI Extraction: Provides accurate interposer-level interconnect model extraction, enabling validation of high-speed signal propagation in the time and frequency domains
- Sigrity SystemSI technology: Automatic construction of complete model-based interconnect topologies used to drive simultaneous switching noise (SSN/SSO) analysis for concise eye-diagram validation
“The new WoW reference flow complements our established InFO and CoWoS chip integration solutions and gives customers more flexibility to use advanced packaging techniques,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Cadence’s strong support for our packaging technologies is instrumental in enabling our mutual customers to achieve the benefits our solutions have to offer.”
“Cadence has a rich history in supporting TSMC’s solutions, and our support for TSMC’s WoW technology lets design engineers deploy the latest packaging techniques so they can get to market faster,” said Tom Beckley, senior vice president and general manager in the Custom IC & PCB Group at Cadence. “Our continued support for TSMC advanced packaging technologies also highlights our close working relationship with TSMC, and we are committed to ensuring customers have access to all the latest technologies to achieve their design goals.”