Cadence Design Systems has introduced a new version of the Incisive functional verification platform. Addressing the challenges associated with intellectual property (IP) block-to-chip and system-on-chip (SoC) verification, the Incisive 13.2 platform offers faster performance with two new engines and additional automation features to speed SoC verification closure.
- For IP block-to-chip verification, enhancements include:
- New Trident engine in the Incisive Formal Verifier and the Incisive Enterprise Verifier, which improves formal analysis performance up to 20X
- New constraint engine in the Incisive Enterprise Simulator that speeds UVM and SystemVerilog testbench simulation, and simulation acceleration with the Palladium platform by up to 10X
- New SystemVerilog support in Incisive Debug Analyzer plus unique UVM debug capabilities and optimised probing in the SimVision debug environment inside Incisive Enterprise Simulator that reduces database size up to 10X
- New IEEE 1647 e unit testing without simulation, reducing debug time for testbench code by 30%
For SoC verification, enhancements include:
- Comprehensive x-propagation support in the Incisive Enterprise Simulator and the Incisive Enterprise Verifier to speed SoC reset and low-power simulations up to 5X
- New support for SystemVerilog IEEE 1800-2012 real number modelling in the Incisive Digital Mixed Signal option for faster mixed-signal simulation over 100X.
“Verification engineers are pressed for time and need strong verification performance. Incisive 13.2 looks to deliver this but also goes beyond raw clocks per second to encompass capabilities from formal apps, debug, and metric aggregation in order to speed verification closure. The combination of automation and integration provides our customers with real gains to ease the challenges of SoC verification,” said Andy Eliopoulos, vice president, research and development, Advanced Verification Solutions at Cadence.