Cadence moves to cut time to market with launch of Palladium XP II Verification Platform

In an move designed to further reduce time to market for both semiconductor and system manufacturers, Cadence Design Systems has introduced the Palladium XP II Verification Computing Platform as part of an enhanced System Development Suite, intended to significantly speeding up hardware and software verification.

The Palladium XP II platform builds on the Palladium XP emulation technology by boosting verification performance by up to 50% and extending its capacity to 2.3 billion gates. With reduced power and increased gate density, customers can now run larger payloads in a smaller footprint, reducing overall cost of ownership. Cadence has also added support for eight new mobile and consumer protocols for simulation acceleration.

As the need for early, fast, and accurate hardware/software verification grows, Cadence has expanded the capabilities of its System Development Suite centred around Palladium, adding patent-pending hybrid technology, which combines the Cadence Virtual System Platform with the Palladium XP series to deliver up to 60X speed-up for embedded OS verification and 10X performance speed-up for hardware/software verification and an embedded test bench for advanced virtualization of system environments, enabling users to verify peripheral software drivers prior to tape-out, resulting in faster post-silicon bring-up.

Commenting Gary Smith, chief analyst at GSEDA, said that the new upgraded hardware capabilities of Palladium XP II platform and the additional advanced use models would help to position Cadence to address the ever increasing system to verification challenges users are currently facing.

www.cadence.com

 

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