Cadence introduces the Tempus Timing Signoff Solution

In a move designed to speed up the development of complex ICs, Cadence Design Systems has introduced the Tempus Timing Signoff Solution, a new static timing analysis and closure tool designed to enable System-on-Chip (SoC) developers to speed timing closure and move chip designs to fabrication quickly. The solution represents a new approach to timing signoff tools that enables customers to shrink timing signoff closure and analysis for faster tapeout while producing designs with less pessimism, area and power consumption.

Commenting Lip-Bu Tan, president and chief executive officer at Cadence, said “Achieving design closure on today’s complex SoCs is a significant challenge to hitting market windows. We developed the Tempus Timing Signoff Solution in collaboration with customers and ecosystem partners to address this challenge.”

The new capabilities introduced in the Tempus Timing Signoff Solution include: the first massively distributed parallel timing engine on the market, which can scale to utilize up to hundreds of CPUs; a parallel architecture that enables the Tempus Timing Signoff Solution to analyze designs in the hundreds of millions of instances without compromising accuracy; a new path-based analysis engine that leverages multi-core processing to reduce pessimism. With its performance advantage, the Tempus Timing Signoff Solution enables broader use of path-based analysis than other solutions; and multi-mode, multi-corner (MMMC) analysis and physically-aware timing closure that leverages multi-threaded and distributed timing analysis.

The Tempus Timing Signoff Solution advanced capabilities can handle designs containing hundreds of millions of cell instances without compromising accuracy. Initial engagements with customers have shown that the Tempus Timing Signoff Solution can achieve timing closure in days on a design that would have taken several weeks with traditional flows.

“Today, the time spent in timing closure and signoff is approaching 40 percent of the overall design implementation flow. Traditional signoff flows have failed to keep pace with the increasing demands of achieving timing closure on complex designs,” said Anirudh Devgan, corporate vice president, Silicon Signoff and Verification, Silicon Realization Group at Cadence. “The Tempus Timing Signoff Solution represents a significant advancement in timing signoff tool innovation and performance, leveraging multi-processing and ECO features to achieve signoff faster than with traditional flows.”


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