Cadence Design Systems has announced that its digital and custom/analog tools have achieved certification from TSMC for its most current version of 10-nanometer (nm) FinFET Design Rule Manual (DRM) and SPICE models.
The Cadence custom/analog and digital implementation and signoff tools have been certified by TSMC on high-performance reference designs in order to provide customers with the fastest path to design closure on the 10nm FinFET process and include:
• Encounter Digital Implementation System and Innovus Implementation System: The Encounter Digital Implementation System has concluded 16-nanometer FinFET Plus (16FF+) V1.0 certification and reached the first milestone of 10nm certification based on the most current DRM and SPICE models. The Encounter Digital Implementation System provides key technology for 16nm and 10nm process enablement and supports floorplanning, placement and routing with integrated color-/pin-access-/variability-aware timing closure, clock tree and power optimisation. Both companies are also working on the certification of Cadence’s recently introduced Innovus Implementation System, with 16FF+ V1.0 certification targeted to be completed by the end of April 2015 and 10nm certification targeted to be completed by June 2015.
• Tempus Timing Signoff Solution: This color-aware timing signoff and signal integrity analysis tool supports 10nm design requirements for waveform propagation, Miller Effect, ultra-low power and variation associated with multi-patterning and FinFET technologies.
• Voltus IC Power Integrity Solution: This cell-based, full-chip power signoff tool supports 10nm design requirements including color-aware layout patterning on power grid and electromigration (EM) rules. Together with other Cadence products, the power signoff solution is able to handle the needed accuracy requirements for the 10nm process in design analysis and optimisation, including IR-drop and EM, IC chip and package co-analysis.
• Voltus-Fi Custom Power Integrity Solution: This SPICE-accurate, transistor-level power signoff tool is used on analog, memory and custom digital IP blocks. It supports 10nm EM/IR drop design requirements down to the device level, including “silicon-width” EM rules.
• Quantus QRC Extraction Solution: This single, unified tool delivers a highly accurate, scalable solution that supports both cell-level and transistor-level extractions during design implementation and signoff. It provides required accuracy with quasi-3D FEOL/MEOL modeling, multi-patterning support, multi-coloring and 3D modeling using the Quantus Field Solver.
• Virtuoso Custom IC advanced-node platform: This industry-leading custom design platform offers comprehensive support for 10nm process requirements including multi-patterning support, 10nm and color-based OpenAccess (OA) constraints, highly matched place-and-route device arrays to account for density-gradient effects, user-assigned mask colors in schematic, cut metal support, color back-annotation flow using Cadence Physical Verification System and 10nm support for Virtuoso Layout Suite for Electrically Aware Design.
• Spectre simulation platform: Spectre Circuit Simulator, Spectre Accelerated Parallel Simulator (APS) and Spectre eXtensive Partitioning Simulator (XPS) deliver fast and accurate circuit simulation with full support of 10nm device models and parasitics.
• Physical Verification System: This full-chip system provides a multi-patterning decomposition and chip-finishing solution that integrates with the Virtuoso Custom IC platform and other Cadence tools to significantly reduce iterations and achieve faster design closure.
• Litho Electrical Analyser: This analyser integrates the TSMC 10nm Layout Dependent Effects (LDE) engine to deliver the 10nm TSMC-certified Virtuoso-LDE flow, which allows custom analog designers to integrate LDE earlier in the design flow and accelerate analog design convergence.
Furthermore, TSMC’s 10nm libraries are created using the Cadence Virtuoso Liberate Characterisation Solution and Spectre Circuit Simulator.
“We collaborated very closely with Cadence on the certification process so our mutual customers can enjoy the performance and power improvements available with advanced FinFET process technologies,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “The certification of Cadence custom/analog and digital implementation and signoff tools ensures design solution readiness for customers to achieve reduced iterations and improved predictability with 10nm FinFET designs.”
“Customers can begin leveraging 10nm FinFET solutions to overcome design complexity and get to market faster, and we are already seeing success with early customer design starts,” said Dr. Chi-Ping Hsu, senior vice president and chief strategy officer for EDA at Cadence. “TSMC and Cadence have had a long history of collaboration that has led to continued advancements in silicon technology, and we plan to work together with our customers to drive innovations based on the latest process technologies.”