Cadence Design Systems has announced that several of its system-on-chip development tools have achieved version 0.1 of design rule manual (DRM) and SPICE model tool certification for TSMC’s 16-nanometer FinFET process. The completion of the early stage tool certification milestone means that advanced node customers can now start developing designs and leveraging the lower power and higher performance benefits required for next-generation mobile platforms.
The tool certification serves as the foundation of design infrastructure for 16-nanometer FinFET technology. The certified Cadence tools are Spectre, Liberate, Virtuoso, Encounter Digital Implementation (EDI) System, Encounter Timing System, Virtuoso Power System, Encounter Power System, Physical Verification System and QRC Extraction. Several Cadence design IP offerings are also available for customer test chips at this advanced node.
In addition, TSMC has certified the production-ready Cadence design flow for its 20-nanometer manufacturing process. Customers can now take advantage of the Cadence solution in order to use the speed, power and area benefits of this advanced node.
The full tool chain was certified at 20 nanometers through the design of an ARM Cortex-A9 processor, and is the first integrated tool certification for TSMC 20SoC process technology. The Cadence tools used are Virtuoso, EDI System, Encounter Timing System, Encounter Power System, Virtuoso Power System, Physical Verification System and QRC Extraction.
“Vertical collaboration at the earliest possible stages of solution development is key to delivering co-optimized solutions,” said Dr. Chi-Ping Hsu, senior vice president of research and development, Silicon Realization Group at Cadence. “TSMC’s certification of Cadence tools for 16-nanometer FinFET and 20-nanometer design underscores our commitment to working with customers to help ensure their success.”
“Our early DRM & SPICE certification, achieved through TSMC’s Open Innovation Platform collaboration model, informs design teams that they can confidently use these Cadence tools for early development of high-performance, low-power 16-nanometer FinFET designs,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “And the certification of the Cadence tools for 20SoC indicates their readiness for this advanced technology process.”