Cadence delivers rapid adoption kit for fast implementation and signoff of new ARM Cortex-R52 CPU

Cadence Design Systems has announced the availability of a Cadence Rapid Adoption Kit (RAK) for the new ARM Cortex-R52 CPU, which targets complex embedded designs for safety applications in markets including automotive, medical and industrial. The Cadence RAK, which consists of a complete digital implementation and signoff flow, is optimised to work with ARM Artisan physical IP and helps designers reach the highest frequency or lowest power during implementation or create a balance between power, performance and area (PPA)all with reduced turnaround times. 

 

The delivery of the new Cadence RAK enables customers using the new ARM Cortex-R52 CPU to:

· Optimise PPA implementation with a full-flow reference methodology incorporating Cadence digital and signoff solutions, including the Genus Synthesis Solution, Innovus Implementation System, Quantus QRC Extraction Solution, Tempus Timing Signoff Solution, Modus Test Solution and multiple Conformal products

· Accelerate implementation of low-power physical designs with the Cadence System-to-GDSII flow

· Implement a highly power-efficient architecture for embedded devices using the complete Cadence low-power, multiple-power-domain flow using IEEE 1801 standard constraints

     

“We designed the ARM Cortex-R52 from the ground up to address functional safety demands in a diversity of applications,” said James McNiven, general manager for CPU and media processing groups, ARM. “Markets with an immediate need for its capability include automotive, industrial and health care as advanced robotics and autonomous vehicles have specific safety-critical requirements. The latest Cadence RAK will support customers using the ARM Cortex-R52, enabling the rapid development and deployment of SoCs.”

 

“We worked closely with ARM to optimise our advanced digital implementation and signoff solutions with the ARM Cortex-R52 CPU, so our customers can start creating innovative embedded designs today,” said Dr. Anirudh Devgan, senior vice president and general manager of the digital and signoff group and the system and verification group at Cadence. “We have thoroughly tested the RAK so that designers can adopt these innovative technologies with confidence and deliver low-power Cortex-R52 devices quickly, enabling early silicon delivery.”

 

www.cadence.com

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