CIE Components in Electronics
Teledyne e2v has made available the EV12AQ600/5 models featuring an integrated license key providing direct access to the novel ADX4 post-processing algorithm developed at SP Devices within the Teledyne group of companies. The ADX4 spur reduction IP dynamically attenuates spurious frequency components resulting from gain, offset and phase mismatches between the four ADC cores. Time-interleaving is a trusted architectural approach to boost ADC sampling rates. However, avoiding resulting spectral artifacts with calibration is especially challenging beyond 10-bit resolutions and in broadband applications.
Applied to the EV12AQ600/5, time-interleaving four cores quadruples the sample rate from 1.6 to 6.4 GS/s. The mismatch errors between the ADC cores reduce spurious free performance. ADX4 delivers a spurious free dynamic range (SFDR) boost of up to 10 dB. That boost is particularly noticeable in broadband applications, and as it requires no hardware design changes is available on demand. The ADX4 code module is simply programmed into the post-processing FPGA. A modification that can even be retrofitted in the field.
About ADC time-interleaving
High-resolution data converters are on an upward trajectory to acquire broader instantaneous bandwidths. A theoretically simple method to achieve higher sampling is by applying time-interleaving to existing cores. Here, multiple ADC cores are clocked on different phases of a common sample clock allowing a higher density of samples of a signal to be acquired. This increased sample density offers a useful performance extension and works well with modest resolutions up to 8-bits in which cross core matching is relatively easy to manage through standard mixed signal calibration and circuit layout schemes.
For 10-bit resolutions and above, especially operating into the gigahertz range, it is increasingly hard to ensure matching. As a result, sampling artifacts arise causing distortion and limiting measured dynamic performance. These high frequency mismatch errors are very challenging to mitigate in the analog design domain. Consider that, for a 6.4 GS/s time-interleaved ADC to achieve 72 dB SNR (the theoretical 12-bit maximum) with a 3 GHz input signal, a cross core phase match of better than 12 fs is required.
Thankfully, over the last two decades, the cost of DSP resources has fallen significantly, now making it economically feasible to take an algorithmic approach to spur reduction. Teledyne SP Devices, the home of high resolution ultra-fast digitizers is well versed in mitigation technologies with experience gathered from several decades work on a broad range of industry leading discrete converters.
Unlike a single or multi-point calibration, ADX4 digital error correction can deliver spur suppression even when the errors vary over frequency. Results are such that the unwanted aliasing spurs are suppressed into the noise floor.
Implementing ADX4
According to the company, it could not be easier to gain ADX4 dynamic enhancements. Via the desired supply chain, customers need only transition their orders across to the -ADX4 options of their EV12AQ600/5 device. Moreover, they need to add the ADX4 module to their Xilinx FPGA code load.
