Altera Quartus II Software v13.1 significantly reduces compiler times

Altera Corporation has released its Quartus II software version 13.1 delivering, what the company claims, an average 30 percent and in some cases up to 70 percent reduction in compile times compared to the previous version. It has achieved this through significant algorithm optimisation and increased parallelization.

The software includes the newly available Rapid Recompile feature for customers making small source code changes on Altera Stratix V FPGA designs. Using Rapid Recompile, customers are able to reuse previous compilation results to preserve performance, without the need for up-front design partitioning, and achieve an additional 50 percent compile time savings.

Commenting Alex Grbic, director, software and IP product marketing said, “With new capabilities and enhancements to the latest version of the Quartus II software, we are delivering a 2X compile time advantage and a 20 percent performance advantage over the competition with our high-end FPGAs.”

Quartus II software version 13.1 also delivers enhancements to its Qsys system integration tool, DSP Builder model based design environment and the Altera SDK for OpenCL.

The Altera Qsys system integration tool saves significant time and effort throughout the FPGA design cycle by automatically connecting together intellectual property (IP) functions and subsystems. Using Qsys, designers can integrate a mix of industry-standard interfaces. In Quartus II software v13.1, Qsys further improves productivity with enhanced system visualization, allowing multiple simultaneous views of the Qsys system making it easier to modify the system, either by adding or connecting components to new a peripherals.

The Altera SDK for OpenCL is now in full production and is the industry’s only FPGA OpenCL solution to pass conformance testing by adhering to the OpenCL specification defined by the Khronos Group. It provides a software-friendly programming environment to design high-performance systems that use FPGAs on Altera’s Preferred Board Partner Program boards or Altera SoCs when using the Altera Cyclone® V SoC development board.

The DSP Builder Design Tool enables system developers to effectively implement high-performance, fixed- and floating-point algorithms into their digital signal processing (DSP) designs. To give engineers more options and flexibility during the design phase, Altera DSP Builder Advanced Blockset systems can now be integrated within MathWorks HDL Coder. Improvements in fast Fourier transform (FFT) processing include variable-sizing of FFTs at run-time and super-sampling FFTs for extremely high data rates of 10GHz, giving unprecedented performance and flexibility options to those implementing this common DSP function.


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