Building on the success of early customer benchmarking results announced earlier this year, Altera Corporation has released early access design software for Stratix 10 FPGAs and SoCs, the industry’s first design software targeting 14-nm FPGAs. Customers can now start their Stratix 10 FPGA designs and experience firsthand the 2X core performance gains they can achieve as a result of the Stratix 10 HyperFlex architecture and the Intel 14 nm Tri-Gate process.
With this design software, Altera has introduced the Hyper-Aware design flow which includes an innovative Fast Forward Compilation capability that allows customers to perform rapid design performance exploration and attain breakthrough levels of performance.
Users are now able to unlock the performance in their designs by taking advantage of the variety of new capabilities available using the HyperFlex architecture to reach breakthrough levels of performance not possible in previous generation FPGA architectures. Developed to enable 2X performance in a customer’s design, Fast Forward Compilation pinpoints performance bottlenecks and provides detailed, step-by-step performance improvement recommendations that a user can rapidly implement. Users also receive Fmax (maximum operating frequency) estimates of their design that can be achieved by applying the recommendations Fast Forward Compilation provides. With this innovative design flow, Fast Forward Compilation gives customers an opportunity to maximize overall design performance made possible by Stratix 10 FPGAs and achieve rapid timing closure.
“The Stratix 10 design tools we are offering today provide customers the fastest path to market for the industry’s highest performance, next-generation FPGAs and SoCs,” said Jordon Inkeles, senior marketing manager, high-end FPGAs, at Altera. “Fast Forward Compilation with the Stratix 10 HyperFlex architecture enables customers to double their performance while simultaneously shaving off weeks to months of engineering development time.”
Previously, in order to achieve high-performance targets, users often needed to undergo multiple, time-consuming design iterations, including trying various design optimizations and re-running full FPGA compiles to determine the effectiveness of design changes. With Fast Forward Compilation, users receive detailed guidance for design optimization and an estimated design Fmax to leverage the HyperFlex architecture. With these insights, customers are better able to make decisions for where to most effectively invest development time to increase their design’s performance and throughput, taking the guesswork out of performance exploration. As a result, Stratix 10 FPGA customers perform fewer design iteration cycles to achieve their performance targets and simplify the path to achieving 2X core performance gains.