AltaSens adopts Cadence Modus Test Solution for mixed-signal image sensor designs

Cadence Design Systems, Inc. has announced that AltaSens has adopted the Cadence Modus Test Solution for its mixed-signal next-generation image sensors. By using the Modus Test Solution in conjunction with other Cadence digital and verification tools on a 90nm process technology, AltaSens successfully met its aggressive test coverage goals while saving several weeks on design convergence.  

 

The Modus Test Solution enabled AltaSens to deliver its first complex digital-on-top (DOT) image sensor design much more efficiently. The Modus Test Solution’s compression logic allowed AltaSens to perform a single pin test, which reduced the impact on the product package and led to reduced test costs. Using the Modus Test Solution’s automatic test pattern generation (ATPG) capabilities, the AltaSens design team was able to meet fault coverage goals rapidly with greater than 98 per cent static coverage, ensuring that the design functioned as intended and that there were no manufacturing defects that could compromise the image sensors.

 

To further ease design development, the Modus Test Solution shares a common user interface with the other Cadence digital and verification tools used by AltaSens, including the Genus Synthesis Solution, the Innovus Implementation System and the Quantus QRC Extraction Solution. This enabled the AltaSens team to handle complex floorplan challenges out of the box. Additionally, the digital flow’s integration with the Cadence Incisive Verification Platform enabled functional verification throughout the design process, speeding time to market.

 

The Cadence Modus Test Solution was very easy to use, and we were able to incorporate it seamlessly with our existing flow to create next-generation image sensors,” said Vikram Murali, principal physical design engineer at AltaSens. “We’ve used competitive test solutions previously and decided to switch to the Cadence test solution for this time-sensitive project because we knew it would involve a minimal learning curve and that we’d spend fewer hours on the design.”

 

The Modus Test Solution enables design engineers to reduce test time by up to 3X, bringing down production test costs and increasing silicon profit margins. The next-generation test solution incorporates a patented, physically aware 2D Elastic Compression architecture that enables compression ratios beyond 400X without impacting design size or routing.

 

www.cadence.com

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