Aldec Introduces Hardware Assisted RTL Simulation Acceleration for Microchip FPGA Designs

Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has introduced a HES-DVM simulation acceleration flow for Microchip’s PolarFire, SmartFusion2 and RTSX/RTAX FPGA designs using Aldec’s HES-MPF500-M2S150 prototyping board.

“Aldec has a long history of developing hardware assisted verification solutions, with our first HES board and simulation acceleration platform released 20 years ago,” said Zibi Zalewski, General Manager of Aldec’s Hardware Division. “We also have a proven track record of developing Microsemi/Microchip FPGA prototyping boards, and it is great that we can combine these areas of expertise to meet today’s verification challenges.”

Simulation acceleration techniques have been around for about two decades, but most products are based on FPGAs from one or two leading FPGA vendors. Usually, it does not matter which FPGA family is used on the simulation acceleration board if the design is coded using synthesizable RTL.

However, growing design complexity, along with shrinking design cycles and shorter time to market, are increasingly taking engineers down the path of re-usable IP blocks from the FPGA vendor, instead of developing RTL code. The drawback is that the designs become dependent on the given FPGA technology, and the re-usable IP blocks usually require far more computational power to simulate than pure RTL code.

Aldec’s HES-DVM overcomes the above challenges and removes a key verification bottleneck. With the latest release of this powerful EDA tool, users of PolarFire, RTAX/RTSX and SmartFusion2 devices wishing to take advantage of Microchip IPs can accelerate their RTL simulations using Aldec’s HES-MPF500-M2S150, which features the largest devices available in both families.

Figure 1: RTL Simulation Acceleration for Microchip FPGAs









Zalewski concludes: “During the 20 years since we introduced HES, the world of digital designs has changed significantly and the need for simulation speeds to increase has grown along with not only design complexity but also the size and features of FPGAs. Our latest release of HES-DVM will be of great benefit to designers using Microchip IPs.”

The 2020.09 software release of HES-DVM is available immediately. To learn more or to evaluate HES-DVM, please visit, e-mail, call +1 (702) 990-4400, or contact one of Aldec’s worldwide distribution partners.

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