32 QFN package for Lattice’s MachXO2 programmable logic devices

The MachXO2 PLD family”s system integration benefits are helping to drive its widespread adoption in a broad range of low density applications that require general purpose I/O expansion, interface bridging and power-up management functions.  Built-in system functions include hardened implementations of widely used I2C and SPI interfaces and a timer/counter in the Embedded Function Block (EFB), providing up to 429 Look Up Tables (LUT) of pre-designed, pre-verified functionality . 

“The widespread adoption of the MachXO2 PLD family in system and consumer applications reflects our customers” eacceptance of low cost, low power, non-volatile PLDs to quickly bring their products to rapidly evolving markets,” said Shakeel Peera, Lattice Director of Strategic Marketing.  “The addition of the 32 QFN package to the MachXO2 portfolio promises to broaden its application in space-constrained, low power applications, including consumer, communications, computing, industrial and medical.”

In order to accelerate development time, over 35 popular reference designs and IP Cores, and the easy-to-use MachXO2 Pico and Control Development Kits, are available for prototyping cost sensitive, low density applications.  Using the preloaded designs provided with the development kit, designers can test within minutes I2C, SPI and UART interfaces.  Engineers can rebuild these demonstration designs using the free downloadable reference design source codes in less than one hour, providing a known good starting point for their own design explorations.  Other reference designs enable designers of system control applications to rapidly prototype typical board control functions such as temperature and current monitoring, power supply sequencing, fault logging, reset distribution and fan control used in system control designs.

Lattice Semiconductor

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