CIE Components in Electronics
Rambus Inc. has announced functional silicon of a double data rate (DDR) server DIMM (dual inline memory module) buffer chipset prototype for the next-generation DDR5 memory technology. This represents a key milestone for Rambus as the industry’s first silicon-proven memory buffer chip prototype capable of achieving the speeds required for the upcoming DDR5 standard.
“We are proud to provide an early path to adoption with the first working buffer chip prototype running at the anticipated performance of next-generation DDR5. This demonstrates our continued dedication to be first to market and remain on the leading edge of industry standards.”
“Data-intensive applications like Big Data analytics and machine learning will be key drivers for the adoption of DDR5, with enterprise close behind,” said Luc Seraphin, senior vice president and general manager of the Rambus Memory and Interfaces Division. “We are proud to provide an early path to adoption with the first working buffer chip prototype running at the anticipated performance of next-generation DDR5. This demonstrates our continued dedication to be first to market and remain on the leading edge of industry standards.”
According to JEDEC, next-generation DDR5 memory will offer improved performance and power efficiency, providing double the bandwidth and density over DDR4. With that, server DIMM chipsets, like registered clock drivers and data buffers, will be critical to enabling higher memory capacities while maintaining peak performance. This server DIMM chip prototype leverages the signal integrity and low-power, mixed-signal design expertise of Rambus to enable development of next-generation solutions for future data centre workloads.
