The power-aware debug module combines support for the United Power Format (UPF) and Common Power Format (CPF) with design comprehension tools for understanding power intent and automated debug techniques to determine whether unexpected design behavior is caused by functional logic or power-related issues. These capabilities are enabled within the Verdi environment for more efficient understanding and debug of low-power system-on-chip (SoC) designs. An early adopter release of the power-aware debug module is already in use by several top-tier global semiconductor companies.

“While CPF and UPF provide a consistent way of describing power intent from RTL design through verification, there have been no power-aware debug tools available at the RTL abstraction,” said Thomas Li, director of product marketing at SpringSoft. “Verdi bridges this power verification gap by providing a universal platform for integrating power formats and innovations with HDL debug automation. Now that it’s easier to visualise, trace, and analyse complex power behaviours in both RTL and UPF/CPF code, engineers can resolve power issues earlier in the process and save valuable verification cycles.”

The Verdi power-aware debug module provides full UPF and CPF source code support with the ability to import and compile data from these power design languages into SpringSoft’s Design Knowledge Database (KDB). This provides a high-level view of power intent that can be correlated with RTL design data also contained in the KDB to give a complete power-aware picture of the design structure. 

An easy-to-use Power Manager browser enables engineers to visualise and annotate power intent in traditional RTL design views (source code, schematic, and waveform). Power-related constraints such as level shifter and switch rules can be easily located for each power domain and correlated to specific RTL design blocks. With the ability to cross probe between power and RTL views, engineers can readily identify the origin of power-related problems.

Leveraging the advanced RTL debug capabilities of the Verdi system, engineers can then track down the root cause of power-related behaviour across RTL and power domains. The paths of signals driven by CPF/UPF code are automatically traced throughout different power domains, so debug is directed to the relevant source. Dynamic power modes/states are annotated in both RTL and power views for seamless tracing between RTL and CPF/UPF code during debug. In addition, the current power status of any signal can be quickly checked and traced to its CPF/UPF source.

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