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SpringSoft has introduced the ProtoLink Probe Visualizer in a move designed to dramatically increase the design visibility and simplify the debugging of FPGA-based prototype boards. The new Probe Visualizer uses patented interconnect innovations and software automation with the industry-leading HDL debug platform to shorten the verification cycle of off-the-shelf or custom-designed prototypes and to maximise their return on investment for early validation of system-on-chip (SoC) designs.
Prototype boards are widely used today to verify that critical design modules or entire systems function correctly because of their fast running speeds and low cost. However, board deployment is often delayed and limited to late in the development cycle because they are inherently difficult to setup and lack the visibility needed to adequately debug designs. The new Probe Visualizer has the ability to probe large numbers of signals over many cycles, easily add/change signals with fast probe ECO flow, and accelerate debug of designs at the register transfer level (RTL) with SpringSoft’s Verdi Automoated Debug System.
SpringSoft is set to target the prototype verification market with the immediate release of Probe Visualizer as the newest addition to its family of verification enhancement products and is being seen as a major milestone as it looks to accelerate the functional closure of complex SoC designs.
“As the capacity and performance of FPGAs get bigger and better, more companies are moving to a FPGA prototyping approach for system-level validation. But, implementation complexity and debug capabilities are still the critical path factors that get in the way of prototype deployment,” said Yu-Chin Hsu, vice president of the Verification Technology and Product Group at SpringSoft. “Probe Visualizer addresses the tremendous verification burden this puts on prototype developers and SoC teams. It uses intuitive, software-based methods to achieve a high level of design visibility and make prototype boards easier to debug starting at the early RTL design stage all the way through final implementation.”
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The Probe Visualizer enables users to expand the number of signals probed from 10s to 1000s, save probe data for millions of clock cycles, and add or change signal probes in minutes without rerunning the entire setup process.
Seamless integration with SpringSoft’s Verdi HDL debug platform means that just a single design compilation is required to use the advanced visualisation and automated tracing capabilities of the Verdi system with the Probe Visualizer. Engineers can view waveforms across multiple FPGAs in order to better analyze design behaviour and find the root cause of bugs in the context of the RTL code with which they are most familiar, cutting debug time in half compared to traditional approaches. They can also simply drag-and-drop additional probed signals if needed from the Verdi environment to the Probe Visualizer. Because probe ECOs are tracked via an integrated revision management system by Probe Visualizer, they also can be quickly traced back to specific configurations as needed during debug.
The Probe Visualizer runs on conventional engineering workstations and consists of an integrated suite of software, hardware and specialized IP that perform FPGA setup, probe instrumentation, and interface tasks. The software automates the pre-partitioned FPGA setup flow and configures each FPGA on the board with a small footprint, soft IP block to extract the pre-selected probed signals. The hardware interface kit provides everything needed to link the workstation running the Probe Visualizer software with the prototype board. It includes a custom ProtoLink interface card that can be connected to either the J-connectors or Mictor connectors commonly found on FPGA prototype boards and a high-speed Fibre channel that connects the interface card to the workstation. The interface card has on-board Probe Memory to store all probe data without requiring the use of FPGA resources.
